EE295 - ASIC Design Using VHDL
Behavioral Modeling - Concurrent Statements
Expressions
Assignment:
- Read Ch 2
- Rewrite the mux4 architecture ( pg 17 ) to eliminate the variable sel.
Hint: This is Not a Tough Assignment, 1 re-written assignment statement
is sufficient to make the point.
- Read Appendix C
The VHDL Language is divided into 2 major groups:
Concurrent and Sequential:
- Concurrency models electrical things accurately
- Sequential processing behaves like a computer program.
In this lecture we review the concurrent constructs of VHDL.
Outline
Simplest Form of Concurrent Assignment
- A <= B; -- value of B gets put onto A's Sensitivity List
- | something that evaluates to a value in the target's type.
- | target of the assignment
The Declaration of signals A and B have triggered the construction
of data structures - lists of driving values.
time(nS): 2 3 5 a list of all the possible transactions
_________ is always maintained
value: A|0|0|1|1
- transaction = change in one of the signals in a signal's sensitivity list
- event = transaction that results in a signal's change of value
- The 'Works':
--Assignment With Delay
D_out <= A and B after 10 nS;
--Conditional Assignment
data_out <= data_in when enable = '1' else 'Z'; -- A tri-state buffer
--Selective Assignment
with sel select --Signal 'sel' Determines Which one of
a <= sig1 after 2 nS when 0, --Several Possible Signals Drives a
sig2 after ( 2 * rise_delay ) nS when 1, -- Value Onto Signal 'a'
sig3 after 7 nS when 2;
Two Basic Delay Models
Inertial Delay
- The Default Mechanism
- Signal values must be present longer then the inherent delay or they 'disappear'.
- Economical Choice for Simulator Resources
- Glitches are not Propogated Throughout the Design
- -BUT-
- fundamentally inaccurate.
Pop Quiz
If our NAND2 cell takes 3 nS to switch..
begin
A <= '0';
A <= '1' after 2 nS;
A <= '0' after 2.5 nS;
U1:NAND2 port map ( A, '1', Z ); --..what value does Z get??
end;
A _______--_____
Z --------------
_______________
| | | | | | | (time)
0 1 2 3
Transport Delay
- Must be Explicitly Activated
- All transactions propogate through an assignment
- Accurate modeling of many devices but the overhead can be prohibitive.
- Use sparingly.
A _______--_____
Z -------------------__---
__________________________
| | | | | | | | | | | | | (time)
0 1 2 3 4 5 6
Z Will now 'Follow' the A Input, Propogating a 0.5 nS Glitch
Simulation Deltas
And now, the magic..
- A mechanism to allow concurrent assignments to be evaluated
correctly before 'real' time increments.
- As a designer simulating a design you will select a time base
for the purposes of displaying signal values. Between 'ticks'
of the 'real' clock delta time advances to permit signal evaluation.
A <= B;
B <= D;
C <= A; -- what's going on here? What Value Does 'C' Get?
D <= '1';
Modeling Multiply Driven Signals
- Signals Driven by More Then One Assignment Statement.
- Typically Bi-directional Busses
- Requires Designer Define a Resolution Function to Describe
How This Particular Signal Behaves For Various Values.
- Many HDLs Fail to Allow For This Important Feature
- A Mechanism for Passing Information into a Model
- May Specify Depth of a RAM, Width of a Bus, Placement of a Cell
- May be Deferred Until Elaboration - Specified
- Through Component Binding.
- Through Configuration.
- Or Optionally Given a Default as in Our Example
- Many Uses in Specifying Critical Information at Instance Time and
Controlling Design Implimentations.
- Partitions Architectures into Sections
-
- Imposes
- Contains a Boolean Guard Expression
- Actually an Implicit Signal
- An Event Triggers Evaluation of All Guarded Assignments
- Models a Device With 'Memory', A FlipFlop or Register
-
-
As Defined By The LRM
- In Order of Precedence - Highest to Lowest
-
- miscellaneous
- abs - Absolute Value of Any Numeric
- not - Inversion of Type Bit
- ** - Exponentiation of Integer or Floating Point to an Integer Power
- multiplying
- *
- /
- mod
- rem
- Integer and Floating Point
- * and / Are Defined For Physical and Integer, Physical and Real, Physical and Physical
- sign
- adding
- +
- -
- For any Numeric Type
-
- &
- concatenation
- For One-Dimensional Arrays
-
relational
- =
- /=
- <
- <=
- >
- >=
- Must Compare Objects of Same Type
- Returns Type Boolean
logical
returns type Bit ( '0' or '1' ) or Boolean ( True or False )
- Type Conversion - Converts Type Between Closely Related Types
- address <= addr_type(row_address & col_address);
- --Address is an Array of Type addr_type and Row and Col_address are
Arrays Whose Lengths Add Up to Address
Syntax Examples:
-- attrib.vhd
-- desc: example syntax of attribute, generic
library cmos;
use cmos.components.and_g; -- or .all to expose the entire library
entity and_gate is generic ( width : integer := 2 );
port ( a_in, b_in : in bit_vector( 0 to width-1);
z : out bit_vector(0 to width-1) );
attribute cell : boolean; --define attribute to pass downstream
attribute cell of entity and_gate is false; --tell design system this is not a
end and_gate; -- library cell.
architecture structural of and_gate is
begin -- The generic contols how many
for i in 0 to width-1 generate -- copies of AND_G get created
U1:AND_G port map ( A1 => a_in(i), B1 => b_in(i), Z1 => z(i) );
end generate;
end structural;
Return to Generic Description
-- process.vhd
-- desc: example use of process statement
architecture sequential of and_gate is
begin
G1:Process ( a_in, b_in ) -- begin sequential processing
begin
case (a_in & b_in) is
when '1'&'1' => z <= '1';
others z <= '0';
end case;
end process;
Return to Process Description
end sequential;
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Copyright 1995, James Swift
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