EE295 - ASIC Design Using VHDL

Introduction

Assignment: Read Ch 1

 We discuss the VHDL Hardware Description Language Introducing
a Few Key Constructs. We discuss the ASIC Design Process.

Outline

What is VHDL?
History of VHDL
Useful VHDL Resources - My 'Top Ten' HotList
What is an ASIC?
Basic VHDL Lexicon

What is VHDL?

VHDL = VHSIC Hardware Description Language
VHSIC = Very High Speed Integrated Circuit
Combines Elements of Programming and Traditional Hardware Design
Supports Complex Hierarchical Design with:
- Strict Rules of Scoping
- Strict Type Enforcement
- Design Library Integrity
Very Rich and Expressive:
- Operator/Function Overloading
```
The + (plus) sign is only meaningful for objects of type integer
or related sub-types in the native language but can be precisely defined
by the designer for *any* types.
```
- User Defined Types -
- Meaningful Enumerated State Values for FSMs
- Binary Enumerated State Values To Meet Implementation Goals
- Bus Values - Valid Instructions for a uProc, Communications Protocol
Technology Independence

History of VHDL

DoD interest in Successful System Integration in an Environment of Independent Contractors using Diverse Design Tools and Methodologies.
'Wood's Hole Conference', A Brain Trust, Best Minds of IBM TI, Intergragh, Consultants. Mission: Define A Super HDL. Result: VHDL7.2.
- Thrived in IBM AS/400, Many Other IBM Designs, Delighted DoD
- Stalled in Marketplace/Academia
Move VHDL into IEEE ( ~= Public_Domain ). Additional Review & Refinements. Result: VHDL-1076
Currently about 8 sub-groups in
- Test ( BSDL - A Test Specific Subset. Mfg Testers Building In Compilers. )
- Synthesis ( Defining Packages of Synthesizable Operators )
- Simulation ( 1164 or MVL9 - Providing Multi-Value Types Representing )
- ASIC Library (VITAL)..
- Investigate These More at the VHDL International Users Foundation(VIUF) Home Page
Groups of Research & Development, CAD Vendors, Technology Providers Conferring on Implementation Details.
Used Extensively in Design Automation Development, Research

Useful VHDL Resources:

VHDL International Users Foundation(VIUF) Links to VI, VITAL, comp.lang.vhdl newsgroup, IEEE worg groups
VHDL International ( VI ) Great Newsletter On-Line
VHDL Syntax in Bachus-Naur Form
Links to VLSI WWW Servers at University of Idaho
A VHDL Tutorial - But Take my Class Anyway!
Consultants:
- TopDown Solutions, Inc VHDL
- Paul Menchini, Menchini Associates, Inc, e-mail: mench@mercury.interpath.net
- Advanced MicroElectronics ASIC Design Center
CAD Vendors:
- TopDown Solutions, Inc MTI V-System Simulator
- Synopsys, Inc Synthesis and Simulation Products
- Cadence, Inc Synthesis & Simulation Products
- Green Mountain Computing Systems Economical DOS-based Simulator
- Accolade Design Automation, Inc Low Cost Tools and Training
Books:
- "The Designer's Guide to VHDL", P Ashenden, Morgan Kaufmann Publishers, San Francisco, 1995, ISBN 1-55860-270-4
- VHDL - 2nd Edition, D Perry, Mcgraw-Hill
- IEEE Language Reference Manual ( LRM ) - 1-800-678-IEEE
  - $50
  - CD ROM May Be Available Soon!
- Magazines:
  - Integrated System Design ( formerly: ASIC & EDA ) - e-mail circ@asic.com

What is an ASIC?

ASIC = Application Specific Integrated Circuit
Implements Custom Function According to Description, not Off-The-Shelf
Described in an HDL ( VERILOG, VHDL ) In an Abstract Technology -Independent Fashion.
Verified Using a Simulator Product - Analogous to Software Debugger
Constructed Out of Logical Function Cells ( AND, OR ) and Re-Usable Macro Building Blocks (ADDERs, REGISTERS )
'Mapped' or Translated Using a Synthesis Product
Implemented in Either Field Programmable, Standard Cell or Gate Array Logic Families.
Connected to External World Through Standardized Protocols and Electrical Interfaces.
Hard Cold Facts:
- Designer Pays CAD Vendors ~$50K - $500K for Design Tools
- Designer Pays NRE ( ~$200K-.5M ) and Per Part
- Under Agreed Upon Production Volumes Levels.
- Cost = f( Performance, Size, Package )
```
 HINT: Size = f( Synthesis Performance ) 
```
Competitive Environment. Entrepreneurial.
Short Time to Market.
Short Successful Product Life Cycle.
Typical Uses:
- Glue logic to connect uProc to external devices: disk drives, CDROM
- Consumer Electronics: Cellular Phones, Games
Entity - Architecture
- Defines a basic design object
- Has a Unique Name
- An Interface
- at least one of several internal representations or architectures.
```
Experienced Engineers Will Intuitively Think of the 
Equivalent Schematic.
```
Component Declaration and instantiation
- Defines another design object
- analogous to a 'socket'
- May Represent Objects ( Entities/Architectures ) But !!
- Not Implicitly Bound to Entity of Same Name
Package - Library - Use
- Package
  - 'Containerizes' Reusable Design Objects. Declarations of:
    - Components
    - Functions
    - Constants
    - Signals
  - Borrowed From The 'C' Programming Model
  - Divided into a header ( ~= .h file ) and body that can be seperately analyzed. The Interface Can Be 'Visible' While 'Hiding' The 'Implementation'.
  - Traditional Mechanism for:
    - ASIC Foundries to Deliver Library Support
    - CAD Vendors to Provide Tool Support
    - Designers to Provide Re-usable Macros
- Library - the Repository that you Analyze VHDL into or Access to Resolve Package References. The Library Statement Declares Your Dependence on a Library for the Design Object that Follows.
- Use - Together with the accompanying library statement specifies the exact design object, package, library combination using ordinary scoping rules.
**NOTE
- VHDL Enforces Library Integrity.
- Any Updates to Libraries You Depend On Require You to Re-Analyze
- The Infamous Time/Date Stamp Mismatch Error Message.
Process
- Actually a Concurrent Statement! Appears in the Body of an Architecture.
- Delimits a Section of Sequential Code
- Optional Sensitivity List Indicates Which Signals 'Wake Up' a Process
- Self-Contained Declarative Region
- Important Time Does Not Increment in a Process - Not Even Delta Time!! Signal Assignments Don't 'Take Place' Until The Process Suspends.
How was the class? Send your comments to jswift@vnet.ibm.com
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Copyright 1995, James Swift
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