Lab #2: Combinational Logic Synthesis

Objectives:

1. To learn how variations in the partitioning of VHDL designs may influence optimizations performed by synthesis tools.
2. To learn how to control optimization of the design to the level of design objects.
3. To gain an appreciation of tradeoffs between area, performance of the design, and the amount of effort required by the synthesis tool required to achieve the optimizations.

Project:

1. Create a design entity for an eight function logic unit with std_logic:
   • Vector inputs X and Y.
   • A three bit function selector input Fselect(0 to 2)
   • Vector output Z
   • Positive edge clocking.
   • The unit is to be N-bits wide, with the X, Y, Z attributes being consistent and defining the width. Include assertions to check that the attributes correspond.
2. Use only concurrent VHDL constructs to write an architecture to implement the following functions:

   	Fselect
           000     Z <= X
           001     Z <= not X
           010     Z <= X and Y
           011     Z <= X nand Y
           100     Z <= X or Y
           101     Z <= X nor Y
           110     Z <= X xor Y
           111     Z <= X xnor Y
   

   There is to be an accumulator register to receive the result of the function computation that drives the output Z.
3. Instantiate the design with a register width of 4, and simulate the design to verify that is works correctly. Include generics specifying values for gate and register delay for simulation purposes.
4. Synthesize the design with opt area -low and again with opt area -high. How much benefit is there in going to the higher level of optimization effort?
5. Rewrite the design as follows: Create a one-bit slice as a separate entity, and instantiate it N times in a FOR-GENERATE statement in the higher level architecture.
6. Synthesize the design from step 5 with opt area -low and again with opt area -high. How much benefit is there in going to the higher level of optimization effort?
7. Find a way to get the synthesis tool to re-synthesize the design so that the Fselect signals are decoded into enable signals that drive tristate outputs from the functions instead of a final stage multiplexor.
8. Note that Fselect(2) controls the inversion of function values (100 = OR, 101=NOR, etc.). Has the synthesis automatically optimized to take advantage of this? If not, modify the design to make this happen.

Report

• For each VHDL description produced, include
  1. a listing of the compiled design,
  2. output of simulation that verifies the design is correct,

• For each synthesis performed, include
  1. a synthesis report that includes area hierarchical and summary information
  2. a gate level schematic generated from the netlist.
• Provide a discussion of the results from each step.

Copyright 1997, Ben M. Huey
Copying this document without the permission of the author is prohibited and a violation of international copyright laws.
Rev. 2/25/97 B. Huey