See Also

The current version of the Quartus^® II software does not support a keep language directive. Instead, you can keep wire and net configurations intact during logic minimization by inserting an LCELL primitive into a VHDL Design File (.vhd) for the design. The LCELL primitive always consumes one logic cell, and is not removed from a design during logic synthesis; as a result, the LCELL primitive can prevent the Logic Synthesizer from minimizing or removing wires and nets from the design.

For example, in the following code, the LCELL primitive prevents the Logic Synthesizer from removing the keep1 and keep2 wires:

SIGNAL keep1;
SIGNAL keep2;
SIGNAL ab_or_cd;

ab_or_cd <= (a AND b) OR (c AND d);
lcell_keep1 : LCELL PORT MAP(ab_or_cd, keep1);
lcell_keep2 : LCELL PORT MAP(ab_or_cd, keep2);

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