Xilinx-to-Altera Design Migration

Xilinx-to-Altera Design Migration...

Page URL: http://www.altera.com/products/software/switching/x/qts-x2a_migration.html

Xilinx-to-Altera Design Migration

The Quartus^® II design software provides a complete and easy-to-use design environment for Altera^® devices. AN 307: Altera Design Flow for Xilinx Users helps designers familiar with Xilinx software learn to perform FPGA design flows quickly using the Quartus II software and to begin targeting Xilinx designs to Altera devices.

Basic Design Flow Comparison
Xilinx ISE Versus Altera Quartus II: Timing Analysis Differences
Step-By-Step Design Flow & Conversion Help

Basic Design Flow Comparison

Altera's design flows can be run from either the command line or through the Quartus II GUI. Figure 1 shows the equivalent Altera versus Xilinx executables for a basic command line flow. Table 1 shows Altera's Quartus II tool equivalents for Xilinx ISE software GUI features.

Figure 1. Typical FPGA Design Flow Addressed by Xilinx & Altera Command Line Executables

Table 1. GUI Tool Equivalents in the Quartus II Software for ISE Features
Feature	Xilinx ISE	Quartus II
Project Creation	New Project	New Project Wizard
Design Constraint Assignments	Constraints Editor and PACE	Quartus II Assignment Editor, I/O Analyzer
Design Entry	HDL Editor Schematic Entry CORE Generator	HDL Editor Schematic Entry MegaWizard^® Plug-In Manager
Synthesis	Xilinx Synthesis Technology (XST) or Third-party EDA Synthesis	Quartus II Integrated Synthesis (QIS) or Third-Party EDA Synthesis
Fitting and Placing the Design Into the FPGA to Meet the User Requirements	Design Implementation: Translate, Map, Place-and-Route	Design Compilation: Analysis & Synthesis, Fitter
Static Timing Analysis on Post-Fitted Design	Xilinx Timing Analyzer and Trace	Quartus II Timing Analyzer
Functional & Timing Simulation	Third-Party Simulation Tools	Third-Party Simulation Tools or Native Quartus II Simulator
Generation of Device Programming File	Bitgen	Assembler
Hardware Verification	ChipScope Pro	SignalTap II
Viewing & Editing Design Placement	Floorplanner or FPGA Editor	Timing Closure Floorplan, Chip Editor
Customization & Generation of Intellectual Property (IP) Cores Through the GUI	Core Generator System	MegaWizard Plug-In Manager
Compilation & Assignment Process for Power Users		Tcl Scripting
Technique Used to Design, Optimize, and Lock Down Nodes One at a Time	Modular Design Flow	LogicLock, Netlist Optimization Options

Xilinx ISE Versus Altera Quartus II: Timing Analysis Differences

In general, the Quartus II timing analyzer calculates all possible register-to-register and complex clock structures using worst-case assumptions. Since many of these complex structures are not analyzed by the Xilinx ISE tool, the comparison can unfairly penalize the Quartus II software’s performance. Adjusting the Quartus II settings to perform equivalent timing analysis to that of ISE will ensure that a fair comparison is made by analyzing the same paths in the circuit. For more information regarding timing analysis differences, visit the Timing Analysis Techniques page.

The Performing Equivalent Timing Analysis Between Altera Quartus II & Xilinx ISE White Paper covers the differences in timing analysis between Xilinx ISE and Altera Quartus II software and outlines a procedure on how to set the tools to provide an equivalent performance comparison.

Step-By-Step Design Flow & Conversion Help

To help designers become familiar with the Quartus II software and to target Xilinx designs to Altera devices, Altera offers AN 307: Altera Design Flow for Xilinx Users . This document consists of two parts:

Part 1: The Quartus II Approach to FPGA Design - Helps Xilinx designers become familiar with the Quartus II software by showing how to perform a basic FPGA design flow using Quartus II procedures instead of the equivalent Xilinx software procedures.
Part 2: Xilinx-to-Altera Design Conversion - Details design file conversion procedures, including:

Identifying design hierarchy
Converting primitives and IP cores
Migrating design constraints