;;;*** altera Configuration interface
pga_dclk	   bit		   p1.0
pga_data	   bit		   p1.1
pga_status	   bit		   p1.2
pga_conf_done	   bit		   p1.3
pga_init_done	   bit		   p1.4
pga_conf	   bit		   p1.5
;;;;;;;;;;;;;; u-com Emulator Test sub-rutine Kevin
;;
;;		jmp	restart
;;
;;;;;;;;;;;;;; u-com Emulator Test sub-rutine Kevin


fpga_init:
		mov	r0,#05
		mov	r1,#03

		clr	pga_dclk
		clr	pga_data

fpga_conf_init_loop:
;;		call	pga_clock
;;		djnz	r0,fpga_conf_init_loop

fpga_conf_init_clr:
		clr	pga_conf
;;		clr	pga_status
fpga_conf_init_clr_loop:
;;		call	pga_clock
		djnz	r1,fpga_conf_init_clr_loop
		nop
		nop
		nop
		nop
		nop
		nop
		setb	pga_conf
;;		setb	pga_status

fpga_status_wait:
		jnb	pga_status,fpga_status_wait

		mov	r0,#0ffh
fpga_fir_data_wait:
		djnz	r0,fpga_fir_data_wait

		mov	dptr,#fpga_code_data_end
		mov	temp1,dpl
		mov	temp2,dph

fpga_data_loading_begin:
		mov	dptr,#fpga_code_data
		clr	a

fpga_data_loading_loop:
		mov	r0,#08
		clr	a
		movc	a,@a+dptr
fpga_data_down_loop:
		rrc	a
		mov	pga_data,c
		setb	pga_dclk
		clr	pga_dclk
;;		call	pga_clock
		djnz	r0,fpga_data_down_loop
		inc	dptr
		mov	a,dpl
		jnb	pga_status,fpga_init
		cjne	a,temp1,fpga_data_loading_loop
		mov	a,dph
		cjne	a,temp2,fpga_data_loading_loop

;;		jnb	pga_conf_done,fpga_init

		mov	r0,#45

fpga_down_init_done:
		setb	pga_dclk
		clr	pga_dclk
		djnz	r0,fpga_down_init_done
		setb	pga_dclk
;;		jnb	pga_init_done,fpga_init

restart:
		       clr     TR0	       ; run tmr 0
		       clr     TR1	       ; TMR 1 DO NOT RUN




;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; FPGA.ASM FILE
;; FILE INCLUDE RUTINE

fpga_code_data:

$include(fpga.ttf)

fpga_code_data_end: