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				Article: DD007 Index Matching the design size to an ASIC or FPGA Author: Tets Maniwa, Integrated System Design Publisher: Integrated System Design Publication Date: June, 1998 Hotlink: ASICColumn9806.html (HTML file, 101 kB) REVIEW: This article provides an overview of the issues and options available to the designer in estimating the size of a design in terms of gate count and I/O.  The author illustrates the constraints placed on design by the size of the target ASIC or FPGA and hence the tradeoffs implied. He then presents some rules of thumb and equations to accurately predict gate count and I/O.  Recomended reading for anyone not already familar with this topic. -- Matt Welland, Qualis Design QUALIS DESIGN CORPORATION 5335 SW Meadows Suite 450 Lake Oswego, OR 97035 USA 503.670.7200 - fax 503.670.0809 ©1997-1998 Qualis Design Corporation