Peter J. Ashenden - supervisor
Sue Tyerman - PhD student
February 1999
Asynchronous implementations of complex high speed processing systems offer several advantages over synchronous implementations, which are currently the norm. These advantages include lower power consumption, lower radio frequency interference and, under some circumstances, high processing speed. The adoption of asynchronous methods has been limited by of a lack of high level synthesis tools, as research into high-level tools for asynchronous systems is still in its infancy. The High-Level Synthesis Project aims to contribute to this important developing field by deriving techniques that may be embodied in future high-level synthesis tools for asynchronous systems.
The semiconductor industry has seen continued growth for some time, based on continuous
improvement in the underlying silicon integrated circuit technology. Most of the growth has
been in the area of digital VLSI and computer-based systems. However, there are two factors
that limit the scalability of current design methods to deal with the increasingly complex
“systems on a chip”.
The first factor relates to the fact that systems currently use a global clock signal to regulate
operation of their internal components. The clock signal is distributed to all parts of an
integrated circuit, and determines the maximum speed of operation of the circuit. Individual
processing operations performed by the circuit must take place within the time of single clock
cycles, and data produced by one part of the circuit must be communicated to another part in
time for the subsequent clock cycle. As the clock cycle time is decreased in line with
technology developments, it is becoming difficult to ensure that the clock signal is distributed
properly and that data transfers occur within cycle-time constraints.
The second factor limiting the scalability of current design methods is the volume of design information that must be dealt with and the number of design decisions that must be made. The key to managing design complexity is a technique called abstraction. It involves dealing with the design at a coarse level of detail (a high level of abstraction) first, then refining each part of the design to a finer level of detail. Current design methods allow a design to be manually refined to the register-transfer level of abstraction, expressed in a hardware description language such as VHDL [1] or Verilog [2], and then allow synthesis tools to be invoked to refine the design further automatically. The limiting factor in this approach is the amount of design work that must be managed to refine the design to the register-transfer level.
These two factors constitute roadblocks that must be removed to enable further development in the semiconductor industry. An important approach to removing the first roadblock is adoption of asynchronous design methods [3]. Rather than using a global clock to synchronise operation of a circuit, asynchronous design allows the presence of data to trigger further processing. Each processing element in the circuit awaits arrival of all of the data it needs, and then produces its result. The resulting data is then transferred to subsequent processing elements, which in turn are triggered to produce their results.
While asynchronous design methods have been known for some time, they have not been widely adopted for a number of reasons. Firstly, they are more difficult to design and test than synchronous systems. Secondly, although they have the potential for improved performance over synchronous systems, the performance improvement is difficult to achieve in practice. Thirdly, the fact of distributing synchronisation amongst circuit elements instead of centralising it with a global clock incurs area overhead in the circuit, and circuit cost is very sensitive to area. However, the increasing difficulty of designing clocked synchronous systems is leading designers to reconsider asynchronous systems, despite their apparent disadvantages. As with many aspects of circuit design, a trade-off must be made, and the balance is now moving in favour of asynchronous designs.
An important approach to removing the second roadblock to design of complex systems is adoption of high-level design using hardware description languages. Furthermore, design at a high level of abstraction must be supported by high-level synthesis, that is, automatic refinement of a design expressed at a high level of abstraction to an implementation at a lower level. There has been much research in the area of high-level synthesis [4], but it is only recently that commercial products have started to appear. As Lin reports, high-level synthesis tools are generally based on a control-data flow graph (CDFG) representation of a design. An important limitation of the research and the commercial products is that they synthesise synchronous implementations from high-level descriptions. Much of the effort in developing such synthesis tools goes into scheduling operations to occur within clock-cycle constraints.
The SUAVE (SAVANT and University of Adelaide VHDL Extensions) project is a collaborative project between Dr Peter Ashenden at Adelaide and Dr Philip Wilsey at the University of Cincinnati, USA. That project has developed extensions to VHDL to improve its support for high-level design. In particular, the extensions include more abstract forms of data modelling and data communication than are currently provided by VHDL. Details of the extensions can be found in published papers [5, 6]. Work is in progress to implement the extensions in VHDL tools developed initially at the University of Cincinnati.
This research addresses the two approaches identified above to removing the road-blocks to design of complex integrated systems. The aim is to develop techniques for high-level synthesis of asynchronous digital integrated systems. In particular, the proposed research will
Whereas synthesis technology for synchronous register-transfer-level designs is relatively mature, there is no similar support for synthesis from high-level designs to asynchronous implementations. What little technology is available for synthesis from high level models is relatively immature and produces synchronous implementations. Research into high-level synthesis for asynchronous systems is in its infancy. The High-Level Synthesis Project aims to contribute to this important developing field by deriving techniques that may be embodied in future high-level synthesis tools for asynchronous systems.
As in the field of register-transfer-level synthesis, not all high-level descriptions that can be expressed in an HDL will be synthesisable. This research aims to determine which language features, when used in prescribed ways, will lead to models that can be synthesised into asynchronous systems. The research will develop a set of modelling guidelines for using VHDL and the SUAVE extensions to write synthesisable high-level models.
The current lack of high-level synthesis tools means that engineers must manually refine high-level models into register-transfer-level implementations. They must then resimulate and compare with previous simulation results to verify correct refinement of behaviour. Furthermore, because current synthesis tools assume clocked synchronisation, the difficulties associated with clocked synchronisation in system-on-a-chip design are not addressed. Were high-level asynchronous synthesis tools available, the burden of manual design refinement would be reduced, and designers would be able to adopt the asynchronous design approach for large-scale systems.
The importance of high-level design is emphasised by the EDA Industry Council, which has identified development of a System Level Design Language as one of the “top ten projects” resulting from its EDA Industry Roadmap [7]. The importance of asynchronous design to the continued development of the semiconductor industry is illustrated by the inclusion of asynchronous elements in emerging high-performance processor designs (for example, the forthcoming Alpha processor designs from Digital).
The research will complement the larger SUAVE research program. In the SUAVE project, the Ashenden and collaborators at the University of Cincinnati have developed extensions to VHDL to support high-level modelling. This work has generated significant interest internationally in the EDA research community and industry. The work has been presented to the IEEE for possible inclusion in future VHDL standards. Work is in progress to implement prototype EDA tools for SUAVE to allow validation experiments for the language extensions.
The research in the High-Level Synthesis Project will be largely undertaken by a doctoral student, Ms. Susan Tyerman, with support from programming staff and Honours students. The doctoral student’s research will initially involve a survey of related research on high-level synthesis and asynchronous system design. (This work has commenced as part of the student's Structured Program.) Next, methods will be devised for synthesising circuits, based on parameterised library components, from a suitable class of high-level models. The class of models identified will form the basis for characterising VHDL and SUAVE models as synthesisable using the techniques devised.
The synthesis techniques devised will be incorporated into a prototype synthesis based on the
analyser that has been developed for SUAVE. Programming staff and Honours students will
extend the analyser to generate CDFGs from the internal representation of the analysed model.
The doctoral student will then use the CDFGs as the basis for model transformations and
synthesis.
The synthesisable HDL subset and the synthesis techniques will be demonstrated by means of a
small number of case-study designs.
[1] IEEE, IEEE Standard VHDL Language Reference Manual, Standard 1076-1993 (New York), 1993.
[2] IEEE, IEEE Standard Description Language Based on the Verilog(TM) Hardware Description Language, Standard 1364-1995 (New York), 1995.
[3] S. Hauck, “Asynchronous Design Methodologies: An Overview,” Proceedings of the IEEE, vol. 83, no. 1, pp. 69-93, 1995.
[4] Y.-L. Lin, “Recent Developments in High-Level Synthesis,” ACM Transactions on Design Automation of Electronic Systems, vol. 2, no. 1, pp. 2-21, 1997.
[5] P. J. Ashenden, P. A. Wilsey, and D. E. Martin, “SUAVE: Extending VHDL to Im-prove Data Modeling Support,” IEEE Design and Test of Computers, vol. 15, no. 2, pp. 34-44, 1998.
[6] P. J. Ashenden and P. A. Wilsey, “Extensions to VHDL for Abstraction of Concurrency and Communication,” Proceedings of Sixth International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS ’98), Montreal, Canada, 1998.
[7] EDA Industry Council, EDA Industry Standards Roadmap 1996 and “Top Ten Projects” Overview, http://www.si2.org/ic/, 1997.