--------------------------------------------------------------------------
--------------------------------------------------------------------------
--	File Name 	: diffeq.v
--	Author(s)	: P. Sridhar
--	Affiliation	: Laboratory for Digital Design Environments
--			  Department of Electrical & Computer Engineering
--			  University of Cincinnati
--	Date Created	: June 1991.
--	Introduction	: Behavioral description of a differential equation
--			  solver written in a synthesizable subset of VHDL.
--	Source		: Written in HardwareC by Rajesh Gupta, Stanford Univ. 
--			  Obtained from the Highlevel Synthesis Workshop
--                        Repository.
--
--	Modified For Synthesis by Jay(anta) Roy, University of Cincinnati.
--	Date Modified	: Sept, 91.
--
--	Disclaimer	: This comes with absolutely no guarantees of any
--			  kind (just stating the obvious ...)
--
--      Acknowledgement : The Distributed Synthesis Systems research at 
--                        the Laboratory for Digital Design Environments,
--                        University of Cincinnati, is sponsored in part 
--                        by the Defense Advanced Research Projects Agency 
--                        under order number 7056 monitored by the Federal 
--                        Bureau of Investigation under contract number 
--                        J-FBI-89-094.
--
--------------------------------------------------------------------------
--------------------------------------------------------------------------
entity diffeq is
  port(aport, dxport : in integer;
       xport, yport, uport : inout integer;
       reset, ready : in bit;
       nxt, over : out bit );
end diffeq;

architecture diffeq of diffeq is

begin

main_proc:process

variable three, five, a, x, y, dx, u, u1, u2, u3, u4, u5, u6, y1 : integer;

begin


if reset = '1' then

 x := 0;
 y := 0;
 u := 0;
 dx := 0;
 a := 0;
 three := 3;
 five := 5;



else

 wait until ready = '1';
 
  x := xport;

  y := yport;

  u := uport;

  dx := dxport;

  a := aport;

  while x < a loop

   u1 := u * dx;
   u2 := five * x;
   u3 := three * y;
   y1 := u * dx;
   x := x + dx;
   u4 := u1 * u2;
   u5 := dx * u3;
   y := y + y1;
   u6 := u - u4;
   u := u6 - u5;

   xport <= x;
   yport <= y;
   uport <= u;
   nxt   <= '1';
   nxt   <= '0';
  end loop;
  
  over <= '1';
  over <= '0';

end if;
   
end process;

end diffeq;