--------------------------------------------------------------------------
--------------------------------------------------------------------------
--	File Name 	: mark1.v
--	Author(s)	: Jay(anta) Roy
--	Affiliation	: Laboratory for Digital Design Environments
--                        Department of Electrical & Computer Engineering
--                        University of Cincinnati
--	Date Created	: October 1990
--	Introduction	: Behavioral description of Mark1 machine written
--			  in a behavioral subset of VHDL.
--	Source		: Original source in ISPS from
--                        Design and Analysis of Instruction Set 
--                        Processors by Barbacci and Siewiorek,
--                        McGraw-Hill 1982
--
--	Disclaimer	: This comes with absolutely no guarantees of any
--			  kind (just stating the obvious ...)
--
--      Acknowledgement : The Distributed Synthesis Systems research at 
--                        the Laboratory for Digital Design Environments,
--                        University of Cincinnati, is sponsored in part 
--                        by the Defense Advanced Research Projects Agency 
--                        under order number 7056 monitored by the Federal 
--                        Bureau of Investigation under contract number 
--                        J-FBI-89-094.
--
--------------------------------------------------------------------------
--------------------------------------------------------------------------
entity mark1 is
end mark1;

use Work.functions.all;

architecture behavior of mark1 is
begin
  process
    type MEM is array(0 to 8191) of BIT_VECTOR(31 downto 0);
    variable Memory : MEM;
    variable CR     : BIT_VECTOR(12 downto 0);
    variable ACC    : BIT_VECTOR(31 downto 0);
    variable PI     : BIT_VECTOR(15 downto 0);
    variable word   : BIT_VECTOR(31 downto 0);
    alias func      : BIT_VECTOR(2 downto 0) is PI(15 downto 13);
    alias addr      : BIT_VECTOR(12 downto 0) is PI(12 downto 0);
    alias PI_word   : BIT_VECTOR(15 downto 0) is word(15 downto 0);
    alias CR_word   : BIT_VECTOR(12 downto 0) is word(12 downto 0);

  begin
    word := Memory(bits_to_int(CR));
    PI := PI_word;

    if func = "000" then
	word := Memory(bits_to_int(addr));
	CR := CR_word;
    elsif func = "001" then
	word := Memory(bits_to_int(addr));
	CR := CR + CR_word;
    elsif func = "010" then
	Memory(bits_to_int(addr)) := ACC;
    elsif func = "100" or func = "101" then
	ACC := ACC - Memory(bits_to_int(addr));
    elsif func = "110" then
	if bits_to_int(ACC) < 0 then
	  CR := CR + 1;
	end if;
    end if;

    CR := CR + 1;
  end process;
end behavior;