--------------------------------------------------------------------------
--------------------------------------------------------------------------
--      File Name       : tseng.v
--      Author(s)       : P. Panchamurti
--      Affiliation     : Laboratory for Digital Design Environments
--                        Department of Electrical & Computer Engineering
--                        University of Cincinnati
--      Date Created    : June 1991.
--      Introduction    : Behavioral description of Tseng's example written
--                        written in a synthesizable subset of VHDL.
--      Source          : Written in HardwareC by Rajesh Gupta, Stanford Univ.
--                        Obtained from the Highlevel Synthesis Workshop
--                        Repository.
--
--      Modified For Synthesis by Jay(anta) Roy, University of Cincinnati.
--      Date Modified   : Sept, 91.
--
--      Disclaimer      : This comes with absolutely no guarantees of any
--                        kind (just stating the obvious ...)
--
--      Acknowledgement : The Distributed Synthesis Systems research at
--                        the Laboratory for Digital Design Environments,
--                        University of Cincinnati, is sponsored in part
--                        by the Defense Advanced Research Projects Agency
--                        under order number 7056 monitored by the Federal
--                        Bureau of Investigation under contract number
--                        J-FBI-89-094.
--
--------------------------------------------------------------------------
--------------------------------------------------------------------------

entity bench is 
  port(v1,v2,v3,v4,v5,v6,v7,v8,v9,v10,v11,v12,v13,v14,v15 : inout integer;
       reset : in bit;
       ready : inout bit);
end bench;

architecture bench of bench is

begin

main_proc:process

variable  v1i,v2i,v3i,v4i,v5i,v6i,v7i,v8i,v9i,v10i,v11i,v12i,v13i,
         v14i,v15i : integer;

variable  tmp,tmp1,tmp2 : integer;

begin

if reset = '1' then

  v1i := 0;
  v2i := 0;
  v3i := 0;
  v4i := 0;
  v5i := 0;
  v6i := 0;
  v7i := 0;
  v8i := 0;
  v9i := 0;
  v10i := 0;
  v11i := 0;
  v12i := 0;
  v13i := 0;
  v14i := 0;
  v15i := 0;


else

  wait until ready = '1';

  v1i := v1;
  v2i := v2;
  v3i := v3;
  v4i := v4;
  v5i := v5;
  v6i := v6;
  v7i := v7;
  v8i := v8;
  v9i := v9;
  v10i := v10;
  v11i := v11;
  v12i := v12;
  v13i := v13;
  v14i := v14;
  v15i := v15;


  v3i := v1i + v2i;
  v5i := v3i - v4i;
  v8i := v3i + v5i;
  --   v14i := v11i & v8i from hardware c
  v1i := v14i;


  v12i := v1i;
  v7i  := v3i * v6i;
  v9i  := v1i + v7i;
  --  v15i := v12i | v9i from hardc
  v2i := v15i;


  v13i := v3i;
  v11i := v10i / v5i;

end if;


-- out_res:process

v1 <= v1i;
v2 <= v2i;
v3 <= v3i;
v4 <= v4i;
v5 <= v5i;
v6 <= v6i;
v7 <= v7i;
v8 <= v8i;
v9 <= v9i;
v10 <= v10i;
v11 <= v11i;
v12 <= v12i;
v13 <= v13i;
v14 <= v14i;
v15 <= v15i;

ready <= '1';
ready <= '0';
ready <= '1';

-- end process out_res;

end process ;
 
end bench;