A Superscalar Version of the DLX Processor

Superscalar DLX Features
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Superscalar DLX Features

- Pipelined, superscalar

• Two instructions per clock
• Branch-Target buffer
• Reorder-Buffer to commit instructions in program order
• Precise exception processing

- Four execution units with Reservation-Station

• Branch-Resolve unit
• Arithmetic-Logic unit
• Multiply-Divide unit
• Load-Store unit

- Write-Buffer
 
- 64 byte Instruction-Cache
 
- 64 byte Data-Cache
 
- 4 entry Instruction-Address-Translation-Buffer, page size: 128 byte
 
- 4 entry Data-Address-Translation-Buffer, page size: 128 byte
 
Note:

• The small caches and address translation buffers increase simulation performance and can be filled up quickly by little test programs.

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You can download PostScript or PDF files of the german documentation. The instruction flow through the pipeline, the design steps and the design unit interfaces are illustrated in many figures.
Compiling the VHDL description enables you to simulate test programs.
An assembler for the DLX processor an other support material is available at http://www.cs.adelaide.edu.au/users/petera/designers-guide/DG-DLX-material.html. (Here)
 
 

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