CS295 - VHDL and ASIC Design Class Home Page

Prepared By: James Swift, Staff Eng, IBM Microelectronics Division

Description:

Students will become familiar with the VHDL language through text readings and lectures following the basic flow of the text. Students will become familiar with the ASIC design process through supplemental readings, lectures and execution of a design project from conceptualization to technology netlist ready for fabrication and described in VHDL.

To Reach Me

email  Internet : jswift@vnet.ibm.com
       Inside IBM :  jswift@btv.ibm.com <-- press here to send mail 
phone: 802-769-6490 (W)
           434-2880 (H)

Text:

 'VHDL - 2nd Edition', D Perry, Mcgraw-Hill

Prerequisites:

• UVM EE131 Fundamentals of Digital Design or equiv Logic Design Course
• UVM CS21 or CS26 Computer Programming or equiv C Programming Course

Course Outline:

1. Introduction - What is VHDL? What is an ASIC? Read Chap 1
2. Project Definition - Establish teams, Define project, Features, Discuss Function vs Cost. Skim Chaps 11 & 12
3. Behavioural Modeling With Concurrent Statements & Expressions - Read Chap 2 + assignment and Appendix C
4. ASIC Methodology
   • Design Tools
   • Review Basic Design Steps
5. Sequential Processing - Read Chap 3 + assignment
6. Data Types - Read Chap 4 + assignment
7. Project Lab - Coding & Analyzing
8. Subprograms - Read Chap 5 + assignment
9. Attributes - Read Chap 6
10. Project Lab - Simulation
11. Simulation Survey - Interpretive vs Compiled Native Code Behavioural, Gate Level, Boolean Equivilance VITAL,
12. Configuration - Read Chap 7
13. Advanced Topics - Read Chap 8
14. Project Lab - Synthesis
15. Synthesis Survey - Technology Mapping, Logic Optimization, Delay Calculation, Area/Performance Trade Off, New IEEE Package, Common Problems Clock Networks
16. IEEE 1076-1993 Updates to the VHDL Language Standard -
17. Testability Survey - Examination of Test techniques and CMOS implimentations. LSSD, Latches vs Flip-Flops, JTAG, ABIST, LBIST VHDL Coding Techniques, Specialized Design Tools, Common Problems.
18. Project Lab - Synthesis continued
19. Project Lab - Final Netlist Creation

Roster:

• Fall 95

Acknowledgements