library dp_32;
use DP_32.DP32_TYPES.all ;
use DP_32.DP32           ;
use DP_32.MEMORY         ;
use DP_32.CLOCK_GEN      ;

entity DP32_TEST is
end DP32_TEST ;

architecture STRUCTURE of DP32_TEST is
   
   component DP32L
      port(D_BUS : inout BUS_BIT_32  bus;
           A_BUS : out   BIT_32         ;
           READ  : out   BIT            ;
           WRITE : out   BIT            ;
           FETCH : out   BIT            ;
           READY : in    BIT            ;
           Ph1   : in    BIT            ;
           Ph2   : in    BIT            ;
           RESET : in    BIT            ) ;
   end component ;
   
   component CLOCK_GENL
      generic(Tpw : TIME ;
              Tps : TIME ) ;
      port(Ph1   : out BIT ;
           Ph2   : out BIT ;
           RESET : out BIT ) ;
   end component ;        
  
   component MEMORYL
      port(D_BUS : inout BUS_BIT_32 bus ;
           A_BUS : in    BIT_32         ;
           READ  : in    BIT            ;
           WRITE : in    BIT            ;
           READY : out   BIT            ) ;
   end component ;         
   
   signal D_BUS : BUS_BIT_32 bus ;
   signal A_BUS : BIT_32         ;
   signal READ  : BIT            ;
   signal WRITE : BIT            ;
   signal FETCH : BIT            ;
   signal READY : BIT            ;
   signal Ph1   : BIT            ;
   signal Ph2   : BIT            ;
   signal RESET : BIT            ;
   signal GUARD : BOOLEAN :=TRUE ;
   
   for CG     : CLOCK_GENL use entity CLOCK_GEN(BEHAVIOUR) ;
   for DP32   : DP32L      use entity DP32(BEHAVIOUR)      ;
   for MEMORY : MEMORYL    use entity MEMORY(BEHAVIOUR)    ;
       
   begin
   
      CG     : CLOCK_GENL
         generic map(8 ns,2 ns)
            port map(Ph1,Ph2,RESET) ;
      DP32   : DP32L
            port map(D_BUS,A_BUS,READ,WRITE,FETCH,READY,Ph1,Ph2,RESET) ;
      MEMORY : MEMORYL
            port map(D_BUS,A_BUS,READ,WRITE,READY) ;      
            
end STRUCTURE ;