--              
--    Package of utilities for the corrected behavioral model of GL85 
--                              (Clone of 8085 microprocessor)
--                                
--              Created by: Celine Poloce (08/1994)
--              MACAO Team of ERM/PHASE
--              Email: yann@erm2.u-strasbg.fr 


library ieee;
use ieee.std_logic_1164.all;


package conversion is

subtype  logic_state is integer range 0 to 1;

function bit2int(a:std_ulogic_vector)return integer;
function bit2int(a:std_ulogic)return integer;

procedure int2bit_sig(signal b:out std_ulogic_vector;entier : in integer);
procedure int2bit(b:out std_ulogic_vector;entier : in integer);
procedure int2bit_sig(signal b:out std_ulogic;entier :in logic_state);
procedure int2bit( b:out std_ulogic;entier :in logic_state);

procedure inc(a:inout std_ulogic_vector);
procedure inc_sig(signal a:inout std_ulogic_vector);
procedure dec (a:inout std_ulogic_vector);
procedure dec_sig(signal a:inout std_ulogic_vector);

end conversion;


package body conversion is

function bit2int(a:std_ulogic_vector) return integer is

variable vtemp :integer:=0;
begin
		for i in a'range loop
			if a(i)='1' then
				vtemp:=vtemp+2**i;

			end if;
		end loop;
	return vtemp;
end bit2int;

function bit2int(a:std_ulogic) return integer is

variable vtemp:integer;
begin
if a='1' then vtemp:=1;
	 else vtemp:=0;
end if;
return vtemp;
end bit2int;

procedure int2bit_sig(signal b:out std_ulogic_vector;entier : in integer) is

variable vtemp:std_ulogic_vector (15 downto 0);
variable x:integer :=entier;

begin
for i in vtemp'reverse_range loop
	if x rem 2=0 then vtemp(i):='0';
		     else vtemp(i):='1';
	end if;
	x:=x/2;
end loop;
for i in b'reverse_range loop
	b(i)<=vtemp(i);
end loop;

end int2bit_sig;

procedure int2bit(  b:out std_ulogic_vector; entier : in integer) is

variable vtemp:std_ulogic_vector (15 downto 0);
variable x:integer;

begin
x:=entier;
for i in b'reverse_range loop
	if x rem 2=0 then 
	  vtemp(i):='0'; 
	else 
	  vtemp(i):='1';
	end if;
	x:=x/2;
end loop;
for i in b'reverse_range loop
	 b(i):=vtemp(i);
end loop;
end int2bit;


procedure int2bit_sig(signal b:out std_ulogic;entier :in logic_state) is

variable vtemp:std_ulogic;
begin
if entier = 0 then vtemp:='0';
	      else vtemp:='1';
end if;
b<=vtemp;
end int2bit_sig;

procedure int2bit( b:out std_ulogic;entier :in logic_state) is

variable vtemp:std_ulogic;
begin
if entier = 0 then vtemp:='0';
	      else vtemp:='1';
end if;
b:=vtemp;
end int2bit;

procedure inc(a:inout std_ulogic_vector) is

variable interm:integer;
begin

interm:=bit2int(a);
interm:=interm +1;
int2bit(a,interm);
end inc;

procedure inc_sig(signal a:inout std_ulogic_vector) is

variable interm:integer;
begin

interm:=bit2int(a);
interm:=interm +1;
int2bit_sig(a,interm);
end inc_sig;


procedure dec (a:inout std_ulogic_vector) is
variable interm :integer;
begin
interm:=bit2int(a);
interm:=interm-1;
int2bit(a,interm);
end dec;

procedure dec_sig(signal a:inout std_ulogic_vector) is
variable interm :integer;
begin
interm:=bit2int(a);
interm:=interm-1;
int2bit_sig(a,interm);
end dec_sig;

end conversion;