--              
--          Test for the corrected behavioral model of GL85 
--                            (Clone of 8085 microprocessor)
--                                
--              Created by: Celine Poloce (08/1994)
--              MACAO Team of ERM/PHASE
--              Email: yann@erm2.u-strasbg.fr 



entity test_i8085erm is
end;

library ieee;
use ieee.std_logic_1164.all;
use work.gene_stimuli;
use work.i8085_erm;

architecture sim of test_i8085erm is

component microproc
port(   x1:in std_ulogic;
	resetout,sod:out std_ulogic;
	sid,trap,rst75,rst65,rst55,intr:in std_ulogic;
	intabar:out std_ulogic;
	address_out:out  std_ulogic_vector(15 downto 0);
	s0,ale,wrbar,rdbar,s1,iombar : out  std_ulogic ;
	ready,resetinbar:in std_ulogic ;
	clkout:out std_ulogic  ;
	hlda:out std_logic  ;
	hold:in  std_ulogic ;
	id:in  std_ulogic_vector(7 downto 0));
end component;

component generateur
port(signal sortie_clk : out std_ulogic;
     signal sortie_init:out std_ulogic_vector(1 to 9);
     signal sortie_action :out std_ulogic_vector(7 downto 0));
end component;

for inst2 : microproc use entity i8085_erm(behavior);
for inst1 : generateur use entity gene_stimuli(archi);

signal init: std_ulogic_vector(1 to 9);
signal id :std_ulogic_vector(7 downto 0);
signal x1:std_ulogic;

-- alias for input signals --

alias sid :std_ulogic is init(1);
alias trap :std_ulogic is init (2);
alias rst75 :std_ulogic is init (3);
alias rst65 :std_ulogic is init (4);
alias rst55 :std_ulogic is init (5);
alias intr :std_ulogic is init (6);
alias ready :std_ulogic is init (7);
alias resetinbar :std_ulogic is init  (8);
alias hold :std_ulogic is init(9);


--      output signals    --

signal resetout,sod,intabar:std_ulogic ;
signal s0,ale,wrbar,rdbar :std_ulogic ;
signal s1,iombar,clkout:std_ulogic ;
signal hlda:std_logic;
signal address_out: std_ulogic_vector(15 downto 0);

begin
inst1 : generateur port map(x1,init,id);

inst2 : microproc port map(x1,resetout,sod,sid,trap,rst75,rst65,rst55,intr,
		  intabar,address_out,s0,ale,wrbar,rdbar,
		  s1,iombar,ready,resetinbar,clkout,hlda,hold,id);

end sim;