Copyright (C) 1988 Intermetrics, Inc.  All rights reserved.
Standard VHDL 1076 Support Environment Version 2.0 - 1 September 1989

%VHDSIM-N-SIGTRAN Signal Tracing turned on 
                   0NS data: 11111 clk: 0 rst: 0 le: 1 cnt: ZZZZZ
                   2NS data: 11111 clk: 0 rst: 0 le: 1 cnt: XXXXX
                   4NS data: 11111 clk: 0 rst: 0 le: 1 cnt: 00000
                  10NS data: 11111 clk: 1 rst: 0 le: 1 cnt: 00000
                  20NS data: 11111 clk: 0 rst: 1 le: 1 cnt: 00000
                  30NS data: 11111 clk: 1 rst: 1 le: 1 cnt: 00000
                  34NS data: 11111 clk: 1 rst: 1 le: 1 cnt: 11111
                  40NS data: 11111 clk: 0 rst: 1 le: 0 cnt: 11111
                  50NS data: 11111 clk: 1 rst: 1 le: 0 cnt: 11111
                  55NS data: 11111 clk: 1 rst: 1 le: 0 cnt: 00000
                  60NS data: 01000 clk: 0 rst: 1 le: 1 cnt: 00000
                  70NS data: 01000 clk: 1 rst: 1 le: 1 cnt: 00000
                  80NS data: 01000 clk: 0 rst: 1 le: 0 cnt: 01000
                  90NS data: 01000 clk: 1 rst: 1 le: 0 cnt: 01000
                  94NS data: 01000 clk: 1 rst: 1 le: 0 cnt: 01001
                 100NS data: 01000 clk: 0 rst: 1 le: 0 cnt: 01001
                 110NS data: 01000 clk: 1 rst: 1 le: 0 cnt: 01001
                 115NS data: 01000 clk: 1 rst: 1 le: 0 cnt: 01010
                 120NS data: 01000 clk: 0 rst: 1 le: 0 cnt: 01010
                 130NS data: 01000 clk: 1 rst: 1 le: 0 cnt: 01010
                 134NS data: 01000 clk: 1 rst: 1 le: 0 cnt: 01011
                 140NS data: 10110 clk: 0 rst: 1 le: 1 cnt: 01011
                 150NS data: 10110 clk: 1 rst: 1 le: 1 cnt: 01011
                 155NS data: 10110 clk: 1 rst: 1 le: 1 cnt: 10110
                 160NS data: 10110 clk: 0 rst: 1 le: 0 cnt: 10110
                 170NS data: 10110 clk: 1 rst: 1 le: 0 cnt: 10110
                 174NS data: 10110 clk: 1 rst: 1 le: 0 cnt: 10111
                 180NS data: 10110 clk: 0 rst: 1 le: 0 cnt: 10111
                 190NS data: 10110 clk: 1 rst: 1 le: 0 cnt: 10111
                 195NS data: 10110 clk: 1 rst: 1 le: 0 cnt: 11000
                 200NS data: 10110 clk: 0 rst: 1 le: 0 cnt: 11000
                 210NS data: 10110 clk: 1 rst: 1 le: 0 cnt: 11000
                 214NS data: 10110 clk: 1 rst: 1 le: 0 cnt: 11001
%VHDSIM-F-ASSERTV Assertion Violation after 220 ns
    at line 8126 in procedure SYS_FINISH at line 8122 in package body <<VERILOG_II>>VERILOG_STD
Simulation Terminated By $FINISH.