---------------------------------------------------------------
-----         Design Unit : mux
---------------------------------------------------------------

library VERILOG; use VERILOG.all;
use VERILOG_STD.all;
use STD.TEXTIO.all;
use WORK.all;

---------- Entity Declaration ----------

entity mux is
    port (
                muxout : OUT WIRE;
                in1 : IN WIRE;
                in0 : IN WIRE;
                sel : IN WIRE
         );
    signal muxout_temp : WIRE;
    signal in1_temp : WIRE;
    signal in0_temp : WIRE;
    signal sel_temp : WIRE;
end mux;


---------- Architecture Body  ----------

architecture arch_mux of mux is
    component AND_GATE
        generic ( strength0 : STRENGTH := STRONG;
                  strength1 : STRENGTH := STRONG;
                  delay1    : INTEGER := NOT_SPECIFIED;
                  delay2    : INTEGER := NOT_SPECIFIED;
                  N         : NATURAL := 2;
                  delay_units : TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  inputs    : in    MVL_VECTOR (1 TO N)
                );
    end component;
    for all: AND_GATE use entity VERILOG.AND_GATE(ARCH_AND_GATE);

    component OR_GATE
        generic ( strength0 : STRENGTH := STRONG;
                  strength1 : STRENGTH := STRONG;
                  delay1    : INTEGER := NOT_SPECIFIED;
                  delay2    : INTEGER := NOT_SPECIFIED;
                  N         : NATURAL := 2;
                  delay_units : TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  inputs    : in    MVL_VECTOR (1 TO N)
                );
    end component;
    for all: OR_GATE use entity VERILOG.OR_GATE(ARCH_OR_GATE);

    component NOT_GATE
        generic ( strength0 : STRENGTH := STRONG;
                  strength1 : STRENGTH := STRONG;
                  delay1    : INTEGER := NOT_SPECIFIED;
                  delay2    : INTEGER := NOT_SPECIFIED;
                  N         : NATURAL := 1;
                  delay_units : TIME := 1 ns
                );
        port    ( outputs   : out   MVL_VECTOR (1 TO N);
                  input     : in    MVL
                );
    end component;
    for all: NOT_GATE use entity VERILOG.NOT_GATE(ARCH_NOT_GATE);

    signal selb, selh, sell : WIRE;
begin

    TEMP_ASSIGN_1: muxout <= muxout_temp;
    TEMP_ASSIGN_2: in1_temp <= in1;
    TEMP_ASSIGN_3: in0_temp <= in0;
    TEMP_ASSIGN_4: sel_temp <= sel;

    n1: NOT_GATE
        generic map (
                      N => 1
                    )
        port map (
                   outputs(1) => selb,
                   input => sel_temp
                 )
    ;

    a1: AND_GATE
        generic map (
                      N => 2
                    )
        port map (
                   output => selh,
                   inputs(1) => in1_temp,
                   inputs(2) => sel_temp
                 )
    ;

    a2: AND_GATE
        generic map (
                      N => 2
                    )
        port map (
                   output => sell,
                   inputs(1) => in0_temp,
                   inputs(2) => selb
                 )
    ;

    o1: OR_GATE
        generic map (
                      N => 2
                    )
        port map (
                   output => muxout_temp,
                   inputs(1) => selh,
                   inputs(2) => sell
                 )
    ;
end arch_mux;



---------------------------------------------------------------
-----         Design Unit : dff
---------------------------------------------------------------

library VERILOG; use VERILOG.all;
use VERILOG_STD.all;
use STD.TEXTIO.all;
use WORK.all;

---------- Entity Declaration ----------

entity dff is
    port (
                q : OUT WIRE;
                qb : OUT WIRE;
                clk : IN WIRE;
                d : IN WIRE;
                rst : IN WIRE
         );
    signal q_temp : WIRE;
    signal qb_temp : WIRE;
    signal clk_temp : WIRE;
    signal d_temp : WIRE;
    signal rst_temp : WIRE;
end dff;


---------- Architecture Body  ----------

architecture arch_dff of dff is
    component NAND_GATE
        generic ( strength0 : STRENGTH := STRONG;
                  strength1 : STRENGTH := STRONG;
                  delay1    : INTEGER := NOT_SPECIFIED;
                  delay2    : INTEGER := NOT_SPECIFIED;
                  N         : NATURAL := 2;
                  delay_units : TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  inputs    : in    MVL_VECTOR (1 TO N)
                );
    end component;
    for all: NAND_GATE use entity VERILOG.NAND_GATE(ARCH_NAND_GATE);

    signal cf, dl, cbf, dbl : WIRE;
begin

    TEMP_ASSIGN_1: q <= q_temp;
    TEMP_ASSIGN_2: qb <= qb_temp;
    TEMP_ASSIGN_3: clk_temp <= clk;
    TEMP_ASSIGN_4: d_temp <= d;
    TEMP_ASSIGN_5: rst_temp <= rst;

    n1: NAND_GATE
        generic map (
                      delay1 => 2,
                      N => 2
                    )
        port map (
                   output => cf,
                   inputs(1) => dl,
                   inputs(2) => cbf
                 )
    ;

    n2: NAND_GATE
        generic map (
                      delay1 => 2,
                      N => 3
                    )
        port map (
                   output => cbf,
                   inputs(1) => clk_temp,
                   inputs(2) => cf,
                   inputs(3) => rst_temp
                 )
    ;

    n3: NAND_GATE
        generic map (
                      delay1 => 1,
                      N => 3
                    )
        port map (
                   output => dl,
                   inputs(1) => d_temp,
                   inputs(2) => dbl,
                   inputs(3) => rst_temp
                 )
    ;

    n4: NAND_GATE
        generic map (
                      delay1 => 1,
                      N => 3
                    )
        port map (
                   output => dbl,
                   inputs(1) => dl,
                   inputs(2) => clk_temp,
                   inputs(3) => cbf
                 )
    ;

    n5: NAND_GATE
        generic map (
                      delay1 => 2,
                      N => 2
                    )
        port map (
                   output => q_temp,
                   inputs(1) => cbf,
                   inputs(2) => qb_temp
                 )
    ;

    n6: NAND_GATE
        generic map (
                      delay1 => 2,
                      N => 3
                    )
        port map (
                   output => qb_temp,
                   inputs(1) => dbl,
                   inputs(2) => q_temp,
                   inputs(3) => rst_temp
                 )
    ;
end arch_dff;



---------------------------------------------------------------
-----         Design Unit : counter
---------------------------------------------------------------

library VERILOG; use VERILOG.all;
use VERILOG_STD.all;
use STD.TEXTIO.all;
use WORK.all;

---------- Entity Declaration ----------

entity counter is
    port (
                cnt : OUT MVL_VECTOR(5 downto 1);
                clk : IN WIRE;
                data : IN MVL_VECTOR(5 downto 1);
                rst : IN WIRE;
                le : IN WIRE
         );
    signal cnt_temp : MVL_VECTOR(5 downto 1);
    signal clk_temp : WIRE;
    signal data_temp : MVL_VECTOR(5 downto 1);
    signal rst_temp : WIRE;
    signal le_temp : WIRE;
end counter;


---------- Architecture Body  ----------

architecture arch_counter of counter is
    component AND_GATE
        generic ( strength0 : STRENGTH := STRONG;
                  strength1 : STRENGTH := STRONG;
                  delay1    : INTEGER := NOT_SPECIFIED;
                  delay2    : INTEGER := NOT_SPECIFIED;
                  N         : NATURAL := 2;
                  delay_units : TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  inputs    : in    MVL_VECTOR (1 TO N)
                );
    end component;
    for all: AND_GATE use entity VERILOG.AND_GATE(ARCH_AND_GATE);

    component XOR_GATE
        generic ( strength0 : STRENGTH := STRONG;
                  strength1 : STRENGTH := STRONG;
                  delay1    : INTEGER := NOT_SPECIFIED;
                  delay2    : INTEGER := NOT_SPECIFIED;
                  N         : NATURAL := 2;
                  delay_units : TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  inputs    : in    MVL_VECTOR (1 TO N)
                );
    end component;
    for all: XOR_GATE use entity VERILOG.XOR_GATE(ARCH_XOR_GATE);

    signal an3, an4, an5 : WIRE;
    signal mcnt, next_cnt : MVL_VECTOR(5 downto 1);
    component dff
        port (
                    q : OUT WIRE;
                    qb : OUT WIRE;
                    clk : IN WIRE;
                    d : IN WIRE;
                    rst : IN WIRE
             );
    end component;
    for all: dff use entity WORK.dff(arch_dff);

    component mux
        port (
                    muxout : OUT WIRE;
                    in1 : IN WIRE;
                    in0 : IN WIRE;
                    sel : IN WIRE
             );
    end component;
    for all: mux use entity WORK.mux(arch_mux);

begin

    TEMP_ASSIGN_1: cnt <= cnt_temp;
    TEMP_ASSIGN_2: clk_temp <= clk;
    TEMP_ASSIGN_3: data_temp <= data;
    TEMP_ASSIGN_4: rst_temp <= rst;
    TEMP_ASSIGN_5: le_temp <= le;

    d1: dff
        port map (
                   cnt_temp(1),
                   next_cnt(1),
                   clk_temp,
                   mcnt(1),
                   rst_temp
                 )
    ;

    d2: dff
        port map (
                   cnt_temp(2),
                   open,
                   clk_temp,
                   mcnt(2),
                   rst_temp
                 )
    ;

    d3: dff
        port map (
                   cnt_temp(3),
                   open,
                   clk_temp,
                   mcnt(3),
                   rst_temp
                 )
    ;

    d4: dff
        port map (
                   cnt_temp(4),
                   open,
                   clk_temp,
                   mcnt(4),
                   rst_temp
                 )
    ;

    d5: dff
        port map (
                   cnt_temp(5),
                   open,
                   clk_temp,
                   mcnt(5),
                   rst_temp
                 )
    ;

    m1: mux
        port map (
                   mcnt(1),
                   data_temp(1),
                   next_cnt(1),
                   le_temp
                 )
    ;

    m2: mux
        port map (
                   mcnt(2),
                   data_temp(2),
                   next_cnt(2),
                   le_temp
                 )
    ;

    m3: mux
        port map (
                   mcnt(3),
                   data_temp(3),
                   next_cnt(3),
                   le_temp
                 )
    ;

    m4: mux
        port map (
                   mcnt(4),
                   data_temp(4),
                   next_cnt(4),
                   le_temp
                 )
    ;

    m5: mux
        port map (
                   mcnt(5),
                   data_temp(5),
                   next_cnt(5),
                   le_temp
                 )
    ;

    x2: XOR_GATE
        generic map (
                      N => 2
                    )
        port map (
                   output => next_cnt(2),
                   inputs(1) => cnt_temp(1),
                   inputs(2) => cnt_temp(2)
                 )
    ;

    a3: AND_GATE
        generic map (
                      N => 2
                    )
        port map (
                   output => an3,
                   inputs(1) => cnt_temp(1),
                   inputs(2) => cnt_temp(2)
                 )
    ;

    x3: XOR_GATE
        generic map (
                      N => 2
                    )
        port map (
                   output => next_cnt(3),
                   inputs(1) => an3,
                   inputs(2) => cnt_temp(3)
                 )
    ;

    a4: AND_GATE
        generic map (
                      N => 3
                    )
        port map (
                   output => an4,
                   inputs(1) => cnt_temp(1),
                   inputs(2) => cnt_temp(2),
                   inputs(3) => cnt_temp(3)
                 )
    ;

    x4: XOR_GATE
        generic map (
                      N => 2
                    )
        port map (
                   output => next_cnt(4),
                   inputs(1) => an4,
                   inputs(2) => cnt_temp(4)
                 )
    ;

    a5: AND_GATE
        generic map (
                      N => 4
                    )
        port map (
                   output => an5,
                   inputs(1) => cnt_temp(1),
                   inputs(2) => cnt_temp(2),
                   inputs(3) => cnt_temp(3),
                   inputs(4) => cnt_temp(4)
                 )
    ;

    x5: XOR_GATE
        generic map (
                      N => 2
                    )
        port map (
                   output => next_cnt(5),
                   inputs(1) => an5,
                   inputs(2) => cnt_temp(5)
                 )
    ;
end arch_counter;



---------------------------------------------------------------
-----         Design Unit : cnt_lab
---------------------------------------------------------------

library VERILOG; use VERILOG.all;
use VERILOG_STD.all;
use STD.TEXTIO.all;
use WORK.all;

---------- Entity Declaration ----------

entity cnt_lab is
end cnt_lab;


---------- Architecture Body  ----------

architecture arch_cnt_lab of cnt_lab is
    signal clk, rst, le, clk_1, rst_1, 
      le_1, clk_2 : MVL := 'X';
    signal data, data_1 : MVL_VECTOR(5 downto 1) := "XXXXX";
    signal cnt : MVL_VECTOR(5 downto 1);
    component counter
        port (
                    cnt : OUT MVL_VECTOR(5 downto 1);
                    clk : IN WIRE;
                    data : IN MVL_VECTOR(5 downto 1);
                    rst : IN WIRE;
                    le : IN WIRE
             );
    end component;
    for all: counter use entity WORK.counter(arch_counter);

    signal SIGNAL_1 : MVL;
begin


    c1: counter
        port map (
                   cnt,
                   clk,
                   data,
                   rst,
                   le
                 )
    ;
    INITIAL_1: process
        variable DISPLAY_1 :  LINE;
    begin
        clk_1 <= '0';
        wait for 0 ns;
        rst_1 <= '0';
        wait for 0 ns;
        le_1 <= '1';
        wait for 0 ns;
        data_1 <= "11111";
        wait for 0 ns;
        wait for 0 ns;
        write (DISPLAY_1, TIME' (sys_time (1 ns) ), RIGHT, 22);
        write (DISPLAY_1, STRING' (" "));
        write (DISPLAY_1, STRING' ("data: "));
        write (DISPLAY_1, MVL_STRING (data));
        write (DISPLAY_1, STRING' (" clk: "));
        write (DISPLAY_1, MVL_STRING (clk));
        write (DISPLAY_1, STRING' (" rst: "));
        write (DISPLAY_1, MVL_STRING (rst));
        write (DISPLAY_1, STRING' (" le: "));
        write (DISPLAY_1, MVL_STRING (le));
        write (DISPLAY_1, STRING' (" cnt: "));
        write (DISPLAY_1, MVL_STRING (cnt));
        writeline (OUTPUT, DISPLAY_1);
        wait for 20 ns;
        rst_1 <= '1';
        wait for 0 ns;
        le_1 <= '1';
        wait for 20 ns;
        le_1 <= '0';
        wait for 20 ns;
        data_1 <= "01000";
        wait for 0 ns;
        le_1 <= '1';
        wait for 20 ns;
        le_1 <= '0';
        wait for 60 ns;
        data_1 <= "10110";
        wait for 0 ns;
        le_1 <= '1';
        wait for 20 ns;
        le_1 <= '0';
        wait for 60 ns;
        sys_finish;
        wait;
    end process INITIAL_1;

    ALWAYS_1: process
    begin
        wait for 10 ns;
        clk_2 <= bit_neg(clk);
    end process ALWAYS_1;

    ALWAYS_2: process
        variable DISPLAY_2 :  LINE;
    begin
        wait until bool (((((data'EVENT) or (clk'EVENT)) or (rst'EVENT)) or (le'EVENT)) or (SIGNAL_1'EVENT));
        wait for 0 ns;
        wait for 0 ns;
        write (DISPLAY_2, TIME' (sys_time (1 ns) ), RIGHT, 22);
        write (DISPLAY_2, STRING' (" "));
        write (DISPLAY_2, STRING' ("data: "));
        write (DISPLAY_2, MVL_STRING (data));
        write (DISPLAY_2, STRING' (" clk: "));
        write (DISPLAY_2, MVL_STRING (clk));
        write (DISPLAY_2, STRING' (" rst: "));
        write (DISPLAY_2, MVL_STRING (rst));
        write (DISPLAY_2, STRING' (" le: "));
        write (DISPLAY_2, MVL_STRING (le));
        write (DISPLAY_2, STRING' (" cnt: "));
        write (DISPLAY_2, MVL_STRING (cnt));
        writeline (OUTPUT, DISPLAY_2);
    end process ALWAYS_2;


    SIGNAL_1 <= align_size (cnt, 1);
    clk <= clk_1 when not clk_1'quiet else 
        clk_2 when not clk_2'quiet else 
        clk;
    rst <= rst_1 when not rst_1'quiet else 
        rst;
    le <= le_1 when not le_1'quiet else 
        le;
    data <= data_1 when not data_1'quiet else 
        data;
end arch_cnt_lab;