--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!--
  --!!                                                                    !!--
  --!!               V E R I L O G _ S T D (G A T E S )   V 1 . 0         !!--
  --!!                                                                    !!--
  --!! The following are the definitions for the Verilog pre-defined      !!--
  --!! gates. The gate definitions are intended for use in verifying the  !!--
  --!! output of VDoc 454 and should not be used for any other purpose or !!-- 
  --!! modified in any way.                                               !!--
  --!!                                                                    !!--
  --!! This program is the Confidential and Proprietary product of        !!--
  --!! Gateway Design Automation Corporation. Any unauthorized use,       !!--
  --!! reproduction, or transfer of this Program is strictly prohibited.  !!--
  --!! Copyright (c) 1989 by Gateway Design Automation Corporation.       !!--
  --!! All Rights Reserved.                                               !!--
  --!!                                                                    !!--
  --!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!--


--############################################################################--
--                                                                            --
--                        VERILOG PREDEFINED GATES ENTITIES                   --
--                                                                            --
--############################################################################--

--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!--
--                             ENTITY DECLARATIONS                            --
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!--
 
    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity AND_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED; 
                  N         : in    NATURAL := 2;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  inputs    : in    MVL_VECTOR (1 TO N) 
                ); 
    end AND_GATE; 

    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity NAND_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED; 
                  N         : in    NATURAL := 2;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  inputs    : in    MVL_VECTOR (1 TO N) 
                );
    end NAND_GATE; 

    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity OR_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED; 
                  N         : in    NATURAL := 2;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  inputs    : in    MVL_VECTOR (1 TO N)
                ); 
    end OR_GATE; 

    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity NOR_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  N         : in    NATURAL := 2;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  inputs    : in    MVL_VECTOR (1 TO N)
                );
    end NOR_GATE; 

    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity XOR_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  N         : in    NATURAL := 2;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  inputs    : in    MVL_VECTOR (1 TO N)
                );
    end XOR_GATE;

    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity XNOR_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  N         : in    NATURAL := 2;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  inputs    : in    MVL_VECTOR (1 TO N)
                );
    end XNOR_GATE;

    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity BUF_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED; 
                  N         : in    INTEGER := 1;
                  delay_units : in   TIME := 1 ns
                );
        port    ( outputs   : out   MVL_VECTOR (1 TO N);
                  input     : in    MVL
                );            
    end BUF_GATE;

    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity NOT_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  N         : in    INTEGER := 1;
                  delay_units : in   TIME := 1 ns
                );
        port    ( outputs   : out   MVL_VECTOR (1 TO N);
                  input     : in    MVL
                );            
    end NOT_GATE;

    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity BUFIF0_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  delay3    : in    INTEGER := NOT_SPECIFIED;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  input     : in    MVL;
                  control   : in    MVL
                );
    end BUFIF0_GATE;


    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity BUFIF1_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  delay3    : in    INTEGER := NOT_SPECIFIED;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  input     : in    MVL;
                  control   : in    MVL
                );
    end BUFIF1_GATE; 


    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity NOTIF0_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  delay3    : in    INTEGER := NOT_SPECIFIED;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  input     : in    MVL;
                  control   : in    MVL
                );
    end NOTIF0_GATE;


    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity NOTIF1_GATE is
        generic ( strength0 : in    STRENGTH := STRONG;
                  strength1 : in    STRENGTH := STRONG;
                  delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  delay3    : in    INTEGER := NOT_SPECIFIED;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  input     : in    MVL;
                  control   : in    MVL 
                );
    end NOTIF1_GATE; 

    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity NMOS_GATE is
        generic ( delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  delay3    : in    INTEGER := NOT_SPECIFIED;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  input     : in    MVL;
                  control   : in    MVL
                );
    end NMOS_GATE;


    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity PMOS_GATE is
        generic ( delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  delay3    : in    INTEGER := NOT_SPECIFIED;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  input     : in    MVL;
                  control   : in    MVL
                );
    end PMOS_GATE;


    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity RNMOS_GATE is
        generic ( delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  delay3    : in    INTEGER := NOT_SPECIFIED;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  input     : in    MVL;
                  control   : in    MVL
                );
    end RNMOS_GATE;


    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity RPMOS_GATE is
        generic ( delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  delay3    : in    INTEGER := NOT_SPECIFIED;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  input     : in    MVL;
                  control   : in    MVL
                );
    end RPMOS_GATE;

    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity CMOS_GATE is
        generic ( delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  delay3    : in    INTEGER := NOT_SPECIFIED;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  input     : in    MVL;
                  ncontrol  : in    MVL;
                  pcontrol  : in    MVL
                );
    end CMOS_GATE;


    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity RCMOS_GATE is
        generic ( delay1    : in    INTEGER := NOT_SPECIFIED;
                  delay2    : in    INTEGER := NOT_SPECIFIED;
                  delay3    : in    INTEGER := NOT_SPECIFIED;
                  delay_units : in   TIME := 1 ns
                );
        port    ( output    : out   MVL;
                  input     : in    MVL;
                  ncontrol  : in    MVL;
                  pcontrol  : in    MVL
                );
    end RCMOS_GATE;

    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity PULLUP_GATE is
        generic ( strength0 : in    STRENGTH := PULL;
                  strength1 : in    STRENGTH := PULL
                );
        port    ( output    : out   MVL );
    end PULLUP_GATE;


    library VERILOG;
    use VERILOG.all;
    use VERILOG_STD.all;

    entity PULLDOWN_GATE is
        generic ( strength0 : in    STRENGTH := PULL;
                  strength1 : in    STRENGTH := PULL
                );
        port    ( output    : out   MVL );
    end PULLDOWN_GATE;  


--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!--
--                         GATES ARCHITECTURES                                --
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!--


    architecture arch_AND_GATE of AND_GATE is

    begin 
        
        process (inputs)
            variable delay: INTEGER;
            variable tern_result: MVL;
            variable curr_result: MVL;
        begin 

            tern_result := red_and(inputs); 
            delay := get_delay2 (delay1, delay2, tern_result); 
            curr_result := get_coerced_val(tern_result, strength0, strength1);

            output <= curr_result after (delay * delay_units);

        end process;

    end arch_AND_GATE; 


    architecture arch_NAND_GATE of NAND_GATE is

    begin 
        
        process (inputs)
            variable delay: INTEGER;
            variable tern_result: MVL;
            variable curr_result: MVL;
        begin 
            tern_result := red_nand(inputs);
            delay := get_delay2 (delay1, delay2, tern_result);
            curr_result := get_coerced_val(tern_result, strength0, strength1);

            output <= curr_result after (delay * delay_units);

        end process;

    end arch_NAND_GATE;


    architecture arch_OR_GATE of OR_GATE is

    begin 
        
        process (inputs)
            variable delay: INTEGER;
            variable tern_result: MVL;
            variable curr_result: MVL;
        begin
            tern_result := red_or(inputs);
            delay := get_delay2 (delay1, delay2, tern_result);
            curr_result := get_coerced_val(tern_result, strength0, strength1);

            output <= curr_result after (delay * delay_units);

        end process;

    end arch_OR_GATE; 


    architecture arch_NOR_GATE of NOR_GATE is

    begin 
        
        process (inputs)
            variable delay: INTEGER;
            variable tern_result: MVL;
            variable curr_result: MVL;
        begin
            tern_result := red_nor(inputs);
            delay := get_delay2 (delay1, delay2, tern_result);
            curr_result := get_coerced_val(tern_result, strength0, strength1);

            output <= curr_result after (delay * delay_units);

        end process;

    end arch_NOR_GATE;


    architecture arch_XOR_GATE of XOR_GATE is

    begin 
        
        process (inputs)
            variable delay: INTEGER;
            variable tern_result: MVL;
            variable curr_result: MVL;
        begin
            tern_result := red_xor(inputs);
            delay := get_delay2 (delay1, delay2, tern_result);
            curr_result := get_coerced_val(tern_result, strength0, strength1);

            output <= curr_result after (delay * delay_units);
        end process;

    end arch_XOR_GATE; 


    architecture arch_XNOR_GATE of XNOR_GATE is

    begin 
        
        process (inputs)
            variable delay: INTEGER;
            variable tern_result: MVL;
            variable curr_result: MVL;
        begin
            tern_result := red_xnor(inputs);
            delay := get_delay2 (delay1, delay2, tern_result);
            curr_result := get_coerced_val(tern_result, strength0, strength1);

            output <= curr_result after (delay * delay_units);

        end process;

    end arch_XNOR_GATE;

  
    architecture arch_PMOS_GATE of PMOS_GATE is

    begin 
        
        process (input, control) 
            variable temp_result: MVL; 
            variable con: MVL ;
            variable inp: MVL ;
            variable temp_strength : STRENGTH;
            variable delay: INTEGER;
            variable result: MVL; 
        begin 
            con := GET_TERN_VAL(control);
            inp := GET_TERN_VAL(input);
            case (con) is
                when '0' =>       
                    result := MODIFY_MOS_STRENGTH(input);
                    delay  := get_delay3 (delay1, delay2, delay3, inp); 

                when '1' =>
                    result := 'Z';
                    delay  := get_delay3 (delay1, delay2, delay3, 'Z'); 
                
                when others => 
                    temp_result := MODIFY_MOS_STRENGTH(input);
                    delay  := get_delay3 (delay1, delay2, delay3, 'X'); 
                    case (inp) is
                        when '0' =>
                          temp_strength := GET_0_STRENGTH(temp_result); 
                          result := GET_COERCED_L
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                        when '1' =>
                          temp_strength := GET_1_STRENGTH(temp_result); 
                          result := GET_COERCED_H
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                        when others =>
                          result := temp_result;
                    end case; 
            end case;

            output <= result after (delay * delay_units);
        end process;

    end arch_PMOS_GATE; 

 
    architecture arch_NMOS_GATE of NMOS_GATE is
    begin 
        
        process (input, control) 
            variable temp_strength : STRENGTH;
            variable temp_result: MVL; 
            variable con: MVL ;
            variable inp: MVL ;
            variable delay: INTEGER;
            variable result: MVL; 
        begin 
            con := GET_TERN_VAL(control);
            inp := GET_TERN_VAL(input);
            case (con) is
                when '0' =>
                    result := 'Z';
                    delay  := get_delay3 (delay1, delay2, delay3, 'Z'); 
                
                when '1' =>       
                    result := MODIFY_MOS_STRENGTH(input);
                    delay  := get_delay3 (delay1, delay2, delay3, inp); 

                when others => 
                    temp_result := MODIFY_MOS_STRENGTH(input);
                    delay  := get_delay3 (delay1, delay2, delay3, 'X'); 
                    case (inp) is
                        when '0' =>
                          temp_strength := GET_0_STRENGTH(temp_result);
                          result := GET_COERCED_L
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                        when '1' =>
                          temp_strength := GET_1_STRENGTH(temp_result); 
                          result := GET_COERCED_H
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                        when others =>
                          result := temp_result;
                    end case; 
            end case;

            output <= result after (delay * delay_units);
        end process;

    end arch_NMOS_GATE; 


    architecture arch_RPMOS_GATE of RPMOS_GATE is
    begin 
        
        process (input, control) 
            variable temp_strength : STRENGTH;
            variable temp_result: MVL; 
            variable con: MVL ;
            variable inp: MVL ;
            variable delay: INTEGER;
            variable result: MVL; 
        begin 
            con := GET_TERN_VAL(control);
            inp := GET_TERN_VAL(input);
            case (con) is
                when '0' =>       
                    result := REDUCE_MOS_STRENGTH(input);
                    delay  := get_delay3 (delay1, delay2, delay3, inp); 

                when '1' =>
                    result := 'Z';
                    delay  := get_delay3 (delay1, delay2, delay3, 'Z'); 
                
                when others => 
                    temp_result := REDUCE_MOS_STRENGTH(input);
                    delay  := get_delay3 (delay1, delay2, delay3, 'X'); 
                    case (inp) is
                        when '0' =>
                          temp_strength := GET_0_STRENGTH(temp_result); 
                          result := GET_COERCED_L
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                        when '1' =>
                          temp_strength := GET_1_STRENGTH(temp_result); 
                          result := GET_COERCED_H
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                        when others =>
                          result := temp_result;
                    end case; 
            end case;

            output <= result after (delay * delay_units);
        end process;

    end arch_RPMOS_GATE; 

 
    architecture arch_RNMOS_GATE of RNMOS_GATE is
    begin 
        
        process (input, control) 
            variable temp_strength : STRENGTH;
            variable temp_result: MVL; 
            variable con: MVL ;
            variable inp: MVL ;
            variable delay: INTEGER;
            variable result: MVL; 
        begin 
            con := GET_TERN_VAL(control);
            inp := GET_TERN_VAL(input);
            case (con) is
                when '0' =>
                    result := 'Z';
                    delay  := get_delay3 (delay1, delay2, delay3, 'Z'); 
                
                when '1' =>       
                    result := REDUCE_MOS_STRENGTH(input);
                    delay  := get_delay3 (delay1, delay2, delay3, inp); 

                when others => 
                    temp_result := REDUCE_MOS_STRENGTH(input);
                    delay  := get_delay3 (delay1, delay2, delay3, 'X'); 
                    case (inp) is
                        when '0' =>
                          temp_strength := GET_0_STRENGTH(temp_result); 
                          result := GET_COERCED_L
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                        when '1' =>
                          temp_strength := GET_1_STRENGTH(temp_result); 
                          result := GET_COERCED_H
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                        when others =>
                          result := temp_result;
                    end case; 
            end case;

            output <= result after (delay * delay_units);
        end process;

    end arch_RNMOS_GATE; 

 

    architecture arch_CMOS_GATE of CMOS_GATE is
    begin 
        
        process (input, ncontrol, pcontrol) 
            variable temp_strength : STRENGTH;
            variable temp_result: MVL; 
            variable pcon: MVL ;
            variable ncon: MVL ;
            variable inp : MVL ;
            variable delay: INTEGER;
            variable result: MVL; 
        begin 
            pcon := GET_TERN_VAL(pcontrol);
            ncon := GET_TERN_VAL(ncontrol);
            inp  := GET_TERN_VAL(input);
            if (pcon = '0' or ncon = '1') then       -- cmos is ON
                  result := MODIFY_MOS_STRENGTH(input);
                  delay  := get_delay3 (delay1, delay2, delay3, inp); 
              elsif (pcon ='1' and ncon = '0') then -- cmos is OFF
                  result := 'Z';
                  delay  := get_delay3 (delay1, delay2, delay3, 'Z'); 
              else                                   -- controls are 'X' or 'Z'
                  temp_result := MODIFY_MOS_STRENGTH(input);
                  delay  := get_delay3 (delay1, delay2, delay3, 'X'); 
                  case (inp) is
                      when '0' =>
                        temp_strength := GET_0_STRENGTH(temp_result); 
                        result := GET_COERCED_L
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                      when '1' =>
                        temp_strength := GET_1_STRENGTH(temp_result); 
                        result := GET_COERCED_H
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                      when others =>
                        result := temp_result;
                  end case;                     
            end if;

            output <= result after (delay * delay_units);
        end process;

    end arch_CMOS_GATE; 

 
    architecture arch_RCMOS_GATE of RCMOS_GATE is
    begin 
        
        process (input, ncontrol, pcontrol) 
            variable temp_strength : STRENGTH;
            variable temp_result: MVL; 
            variable pcon: MVL ;
            variable ncon: MVL ;
            variable inp : MVL ;
            variable delay: INTEGER;
            variable result: MVL; 
        begin 
            pcon := GET_TERN_VAL(pcontrol);
            ncon := GET_TERN_VAL(ncontrol);
            inp  := GET_TERN_VAL(input);
            if (pcon = '0' or ncon = '1') then       -- rcmos is ON
                  result := REDUCE_MOS_STRENGTH(input);
                  delay  := get_delay3 (delay1, delay2, delay3, inp); 

              elsif (pcon ='1' and ncon = '0') then -- rcmos is OFF
                  result := 'Z';
                  delay  := get_delay3 (delay1, delay2, delay3, 'Z'); 

              else                                   -- controls are 'X' or 'Z'
                  temp_result := REDUCE_MOS_STRENGTH(input);
                  delay  := get_delay3 (delay1, delay2, delay3, 'X'); 
                  case (inp) is
                      when '0' =>
                        temp_strength := GET_0_STRENGTH(temp_result);
                        result := GET_COERCED_L
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                      when '1' =>
                        temp_strength := GET_1_STRENGTH(temp_result);
                        result := GET_COERCED_H
                             (temp_strength(7), temp_strength(6),
                              temp_strength(5), temp_strength(4),
                              temp_strength(3), temp_strength(2),
                              temp_strength(1), temp_strength(0));
                      when others =>
                        result := temp_result;
                  end case; 
            end if;

            output <= result after (delay * delay_units);
        end process;

    end arch_RCMOS_GATE; 

    architecture arch_BUF_GATE of BUF_GATE is
    begin 
        
        process (input) 
            variable value: MVL;
            variable results: MVL_VECTOR(N-1 downto 0);
            variable delay: INTEGER;
            variable in_new: MVL ;
        begin 

            in_new := GET_TERN_VAL(input);
            delay := get_delay2 (delay1, delay2, in_new);
            value := get_coerced_val (in_new, strength0, strength1); 
            results := fill_mvl_vector(value, N);

            outputs <= results after (delay * delay_units);

        end process;

    end arch_BUF_GATE; 


    architecture arch_NOT_GATE of NOT_GATE is
    begin 
        
        process (input) 
            variable value: MVL;
            variable results: MVL_VECTOR(N-1 downto 0); 
            variable delay: INTEGER;
            variable in_new: MVL ;
            variable in_new_vector : MVL_VECTOR(1 to 1);
            variable out_new: MVL;
        begin 

            in_new := GET_TERN_VAL(input);
            in_new_vector(1) := (in_new);
            out_new := log_not(in_new_vector); -- output is inverted

            delay := get_delay2 (delay1, delay2, out_new);
            value := get_coerced_val (out_new, strength0, strength1); 
            results := fill_mvl_vector(value, N);

            outputs <= results after (delay * delay_units);

        end process;

    end arch_NOT_GATE; 

   


    architecture arch_BUFIF0_GATE of BUFIF0_GATE is
    begin 
        
        process (input, control) 
            variable con: MVL ;
            variable inp: MVL ;
            variable delay: INTEGER;
            variable result: MVL; 
        begin

            con := GET_TERN_VAL(control);
            inp := GET_TERN_VAL(input);
            case (con) is
                when '0' =>
                    delay  := get_delay3 (delay1, delay2, delay3, inp); 
                    result := get_coerced_val(inp, strength0, strength1);

                when '1' =>
                    result := 'Z';
                    delay  := get_delay3 (delay1, delay2, delay3, 'Z'); 
                
                when others => 
                    delay  := get_delay3 (delay1, delay2, delay3, 'X'); 
                    case (inp) is
                        when '0' =>
                          result := GET_COERCED_L
		             (strength0(7),strength0(6),strength0(5),
                             strength0(4),strength0(3),strength0(2),
                             strength0(1),strength0(0));
                        when '1' =>
                          result := GET_COERCED_H
		             (strength1(7),strength1(6),strength1(5),
                             strength1(4),strength1(3),strength1(2),
                             strength1(1),strength1(0));
                        when others => 
                          result := get_coerced_val('X', strength0, strength1); 
                    end case; 
            end case;

            output <= result after (delay * delay_units);
        end process;

    end arch_BUFIF0_GATE; 


    architecture arch_BUFIF1_GATE of BUFIF1_GATE is
    begin 
        
        process (input, control) 

            variable con: MVL ;
            variable inp: MVL ;
            variable delay: INTEGER;
            variable result: MVL; 
        begin

            con := GET_TERN_VAL(control);
            inp := GET_TERN_VAL(input);
            case (con) is
                when '0' =>
                    result := 'Z';
                    delay  := get_delay3 (delay1, delay2, delay3, 'Z'); 

                when '1' =>
                    delay  := get_delay3 (delay1, delay2, delay3, inp); 
                    result := get_coerced_val(inp, strength0, strength1);
                
                when others => 
                    delay  := get_delay3 (delay1, delay2, delay3, 'X'); 
                    case (inp) is
                        when '0' =>
                          result := GET_COERCED_L
		             (strength0(7),strength0(6),strength0(5),
                             strength0(4),strength0(3),strength0(2),
                             strength0(1),strength0(0));
                        when '1' =>
                          result := GET_COERCED_H
		             (strength1(7),strength1(6),strength1(5),
                             strength1(4),strength1(3),strength1(2),
                             strength1(1),strength1(0));
                        when others => 
                          result := get_coerced_val('X', strength0, strength1); 
                    end case; 
            end case;

            output <= result after (delay * delay_units);
        end process;

    end arch_BUFIF1_GATE;


    architecture arch_NOTIF0_GATE of NOTIF0_GATE is
    begin 
        
        process (input, control) 

            variable con: MVL ;
            variable inp: MVL ;
            variable inp_vector : MVL_VECTOR(1 to  1);
            variable delay: INTEGER;  
            variable outp: MVL ;
            variable result: MVL; 
        begin 

            con := GET_TERN_VAL(control);
            inp := GET_TERN_VAL(input);
            inp_vector(1) := (inp);            
            outp := log_not(inp_vector);
            case (con) is
                when '0' =>
                    delay  := get_delay3 (delay1, delay2, delay3, outp); 
                    result := get_coerced_val(outp, strength0, strength1);

                when '1' =>
                    result := 'Z';
                    delay  := get_delay3 (delay1, delay2, delay3, 'Z'); 
                
                when others => 
                    delay  := get_delay3 (delay1, delay2, delay3, 'X'); 
                    case (inp) is
                        when '0' =>              -- output is inverted
                          result := GET_COERCED_H
		             (strength1(7),strength1(6),strength1(5),
                             strength1(4),strength1(3),strength1(2),
                             strength1(1),strength1(0));
                        when '1' =>              -- output is inverted
                          result := GET_COERCED_L
		             (strength0(7),strength0(6),strength0(5),
                             strength0(4),strength0(3),strength0(2),
                             strength0(1),strength0(0));
                        when others => 
                          result := get_coerced_val('X', strength0, strength1); 
                    end case; 
            end case;

            output <= result after (delay * delay_units);
        end process;

    end arch_NOTIF0_GATE; 


    architecture arch_NOTIF1_GATE of NOTIF1_GATE is
    begin 
        
        process (input, control) 

            variable con: MVL ;
            variable inp: MVL ;
            variable inp_vector : MVL_VECTOR (1 to 1);
            variable delay: INTEGER; 
            variable outp: MVL ;
            variable result: MVL; 
        begin

            con := GET_TERN_VAL(control);
            inp := GET_TERN_VAL(input);
            inp_vector(1) := (inp);
            outp := log_not(inp_vector);
            case (con) is
                when '0' =>
                    result := 'Z';
                    delay  := get_delay3 (delay1, delay2, delay3, 'Z'); 

                when '1' =>
                    delay  := get_delay3 (delay1, delay2, delay3, outp); 
                    result := get_coerced_val(outp, strength0, strength1);
                
                when others => 
                    delay  := get_delay3 (delay1, delay2, delay3, 'X'); 
                    case (inp) is
                        when '0' =>              -- output is inverted
                          result := GET_COERCED_H
		             (strength1(7),strength1(6),strength1(5),
                             strength1(4),strength1(3),strength1(2),
                             strength1(1),strength1(0));
                        when '1' =>              -- output is inverted
                          result := GET_COERCED_L
		             (strength0(7),strength0(6),strength0(5),
                             strength0(4),strength0(3),strength0(2),
                             strength0(1),strength0(0));
                        when others => 
                          result := get_coerced_val('X', strength0, strength1); 
                    end case; 
            end case;

                output <= result after (delay * delay_units);
        end process;

    end arch_NOTIF1_GATE; 

 
    architecture arch_PULLUP_GATE of PULLUP_GATE is

    begin                             
        output <= GET_MVL_1  
		             (strength1(7),strength1(6),strength1(5),
                             strength1(4),strength1(3),strength1(2),
                             strength1(1),strength1(0));
    end arch_PULLUP_GATE; 


    architecture arch_PULLDOWN_GATE of PULLDOWN_GATE is
    begin                             
        output <= GET_MVL_0  
		             (strength0(7),strength0(6),strength0(5),
                             strength0(4),strength0(3),strength0(2),
                             strength0(1),strength0(0));
    end arch_PULLDOWN_GATE;