Entity DotTest is end;

library vdeg_portable,vdeg_benchmark;
use vdeg_portable.types.all;
use work.all;

architecture DataFlow of DotTest is


        -- This architecture connects signal of the three dot
        -- subtypes to a signal of type Logic4. It tests the
        -- three resolution functions for all combinations
        -- of two drivers.

type DotTable is Array (0 to 3) of Logic4;

Constant Table : DotTable := ('X','Z','0','1');

Signal andtest0,andtest1,anddot :DotAnd;
Signal ortest0,ortest1,ordot    :DotOr;
Signal xtest0,xtest1,xdot       :DotX;
Signal andout,orout,xout        :Logic4;
Signal counter                  :Natural;

begin

	counter <= counter + 1 after 1 ns;  -- simulation control counter
	assert counter < 16
		severity error;
		
		
	process (counter)

		-- process to index through all combinations

	variable Index0,Index1 :Natural;
	begin
	   
	   if Index0 < 3 then 
		Index0 := Index0 + 1;
	   elsif Index1 < 3 then
		Index1 := Index1 +1;
		Index0 := 0;
	   else
		Index0 := 0;
		Index1 := 0;
	   end if;

	   	   andtest0 <= Table(Index0);
	   	   ortest0  <= Table(Index0);
	   	   xtest0   <= Table(Index0);

	   	   andtest1 <= Table(Index1);
	   	   ortest1  <= Table(Index1);
	   	   xtest1   <= Table(Index1);
	end process;

	anddot <= andtest0;
	anddot <= andtest1;

	ordot <= ortest0;
	ordot <= ortest1;

	xdot <= xtest0;
	xdot <= xtest1;
	
	andout <= anddot;
	orout  <= ordot;
	xout   <= xdot;
end DataFlow;

--------------------------------------------------------------

library vdeg_portable,vdeg_benchmark;
use vdeg_portable.types.all;
use work.all;

architecture structure of DotTest is


        -- This architecture connects signal of the three dot
        -- subtypes to inputs of components of type Logic4.
        -- In this case simple buffers are used to connect to
        -- the resolved signals;

type DotTable is Array (0 to 3) of Logic4;

Constant Table : DotTable := ('X','Z','0','1');

Signal andtest0,andtest1,anddot :DotAnd;
Signal ortest0,ortest1,ordot    :DotOr;
Signal xtest0,xtest1,xdot       :DotX;
Signal andout,orout,xout :Logic4;
Signal counter :Natural;

component  BUF
    generic (tPLH:  Time    := 0ns;         -- rise prop. delay
             tPHL:  Time    := 0ns;         -- fall prop. delay
             tW:    Time    := 0ns);        -- min. pulse width
    port    (A: in  Logic4;
             Z: out Logic4);
    end component;
for all: BUF use entity vdeg_portable.buf(vdeg);
begin

	counter <= counter + 1 after 1 ns;    -- simulation control counter
	assert counter < 16
		severity error;
	process (counter)

		-- process to index through all combinations

	variable Index0,Index1 :Natural;
	begin
	   
	   if Index0 < 3 then 
		Index0 := Index0 + 1;
	   elsif Index1 < 3 then
		Index1 := Index1 +1;
		Index0 := 0;
	   else
		Index0 := 0;
		Index1 := 0;
	   end if;

	   	   andtest0 <= Table(Index0);
	   	   ortest0  <= Table(Index0);
	   	   xtest0   <= Table(Index0);

	   	   andtest1 <= Table(Index1);
	   	   ortest1  <= Table(Index1);
	   	   xtest1   <= Table(Index1);
	end process;

	anddot <= andtest0;
	anddot <= andtest1;

	ordot <= ortest0;
	ordot <= ortest1;

	xdot <= xtest0;
	xdot <= xtest1;
	
--	andout <= anddot;
--	orout  <= ordot;
--	xout   <= xdot;

--	Replace assignments with a buffer

bof0:  BUF port map (anddot,andout);
bof1:  BUF port map (ordot,orout);
bof2:  BUF port map (xdot,xout);

end structure;

------------------------------------------------------------------
------------------------------------------------------------------
------------------------------------------------------------------
Entity BusTest is end;

library vdeg_portable,vdeg_benchmark;
use vdeg_portable.types.all;
use work.all;

architecture DataFlow of BusTest is

type BusTableAnd is Array (0 to 3) of BusAnd(1 downto 0);
type BusTableOr  is Array (0 to 3) of BusOr(1 downto 0);
type BusTableX   is Array (0 to 3) of BusX(1 downto 0);

Constant AndTable : BusTableAnd := ("XZ","Z0","01","1X");
Constant OrTable  : BusTableOr  := ("XZ","Z0","01","1X");
Constant XTable   : BusTableX   := ("XZ","Z0","01","1X");

Signal andtest0,andtest1,andbus :BusAnd(1 downto 0);
Signal ortest0,ortest1,orbus    :BusOr(1 downto 0);
Signal xtest0,xtest1,xbus       :BusX(1 downto 0);
Signal andout,orout,xout :Vector4(1 downto 0);
Signal counter :Natural;

begin

	counter <= counter + 1 after 1 ns;
	assert counter < 16
		severity error;
	process (counter)

		-- process to index through all combinations

	variable Index0,Index1 :Natural;
	begin
	   
	   if Index0 < 3 then 
		Index0 := Index0 + 1;
	   elsif Index1 < 3 then
		Index1 := Index1 +1;
		Index0 := 0;
	   else
		Index0 := 0;
		Index1 := 0;
	   end if;

	   	   andtest0 <= AndTable(Index0);
	   	   ortest0  <= OrTable(Index0);
	   	   xtest0   <= XTable(Index0);

	   	   andtest1 <= AndTable(Index1);
	   	   ortest1  <= OrTable(Index1);
	   	   xtest1   <= XTable(Index1);

	end process;

	andbus <= andtest0;
	andbus <= andtest1;

	orbus <= ortest0;
	orbus <= ortest1;

	xbus <= xtest0;
	xbus <= xtest1;
	
	        -- Type Conversion Functions are required
	        
	andout <= Vector4(andbus);
	orout  <= Vector4(orbus);
	xout   <= Vector4(xbus);


end DataFlow;