use work.all;
Entity rf_bench is end;

library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Architecture test of rf_bench is

	Component  Reg_File
	        port (A_Address,B_Address,B_Data : in   Vector4(3 downto 0);
	          Clock,RFile_Enable         : in   Logic4;
	          Abus,Bbus                  : out  Vector4(3 downto 0));
	      end component;

for RF1:Reg_File use entity  vdeg_benchmark.Reg_File(DataFlow);


	Signal addgen,A_ADR,B_ADR,DataIn    :Vector4(3 downto 0):="0000";
	Signal Aout,Bout	  :Vector4(3 downto 0);
	Signal CLK        :Logic4 := '0';
	Signal WritePulse :Logic4 := '1';
	Signal Counter                          :Natural;
	Signal IncAddress                   :Vector4(4 downto 0):="00000";
        Signal ClockEdge :Boolean;
begin

CLK <= not(CLK) after 20 ns;
ClockEdge <= (CLK='1') and not Clk'Stable;

DataGenerator:	Block(ClockEdge)
        begin

		IncAddress <= guarded increment(addgen)  after 10 ns;
		A_ADR   <= IncAddress(3 downto 0);
		addgen  <= A_ADR  after 1 ns;
		B_ADR  <= not(addgen) after 3ns;
                 
		DataIn <= A_ADR after 1 ns;

--	 Counter is a Natural incremented for sim Control;
		Counter <= guarded Counter + 1 after 2ns;
end block DataGenerator;

	process (CLK)

	begin
		if Counter < 16 then 
			WritePulse <= '1';
		else
			WritePulse <= '0';
		end if;
	end process;

-- Instantiation of the Rfile(s)

	RF1:  Reg_File
	        port map (A_ADR,B_ADR,DataIn,CLK,WritePulse,Aout,Bout);


	assert counter < 64
		report "End of Simulation reached"
		severity error;
end Test;



library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Entity Decode_bench is end;


library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Architecture test of Decode_bench is

	Signal In_Vec :Vector4(3 downto 0) := "0000";
	Signal ovector:Vector4(4 downto 0) := "00000";
	Signal Out_Vec:BusAnd(15 downto 0);
	Signal Counter : Natural := 0;

Component Decode_4_to_16
	port(vector :in Vector4(3 downto 0);
	     DecodeLines :out BusAnd(15 downto 0));
end Component;

-------------  Configuration Section
    
for All:Decode_4_to_16 use entity  vdeg_benchmark.Decode_4_to_16(Structure);

begin

	Counter <= counter + 1 after 10ns;
	In_Vec  <= ovector(3 downto 0);
	ovector <= increment(In_Vec) after 10ns;

DCode: Decode_4_to_16 port map(In_Vec,Out_Vec);

	Assert Counter < 17
		Report " Termination count reached End of Simulation"
		Severity error;
end test;