------------------------------------------------------------------------------
--
-- This package was developed by CAD Language Systems, Inc. as part of an
-- effort to define a basis for portable VHDL models.  It has been submitted
-- to the VHDL Design Exchange Group (VDEG) to be considered as the basis for
-- a set of industry-wide, portable modeling conventions.
--
-- This package defines a set of components that can be supported on many
-- subset simulators.
--
-- HISTORY:
--	21-AUG-89 PJM	Per SSS, added a clock port to the JK flip-flop.
--	27-JUL-89 PJM	Modified to use independent formal subelement
--			association only when necessary and to improve
--			formatting.
--	26-MAY-89 PJM	Modified to improve comments, fix the modes of some of
--			the ports on the flip-flops, and to change generics of
--			type Delay to be of type Time (the timing
--			specification functions in package
--			VDEG_Portable.Timing can be used to supply min-nom-max
--			timing to these generics).
--	11-MAY-89 PJM	Updated to reflect May 9-10 VDEG consensus.
--	22-APR-89 SSS	Created.
--
------------------------------------------------------------------------------


library VDEG_Portable;
use VDEG_Portable.Types.all;

package Components is

    component AND2
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component AND3
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component AND4
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         D:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component ANDn
	generic (n:	in	Positive;
	         tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Vector4 (1 to n);
	         Z:	out	Logic4);
    end component;

    component NAND2
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component NAND3
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component NAND4
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         D:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component NANDn
	generic (n:	in	Positive;
	         tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Vector4 (1 to n);
	         Z:	out	Logic4);
    end component;

    component OR2
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component OR3
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component OR4
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         D:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component ORn
	generic (n:	in	Positive;
	         tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Vector4 (1 to n);
	         Z:	out	Logic4);
    end component;

    component NOR2
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component NOR3
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component NOR4
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         D:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component NORn
	generic (n:	in	Positive;
	         tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Vector4 (1 to n);
	         Z:	out	Logic4);
    end component;

    component XOR2
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component XOR3
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component XOR4
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         D:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component XORn
	generic (n:	in	Positive;
	         tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Vector4 (1 to n);
	         Z:	out	Logic4);
    end component;

    component XNOR2
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component XNOR3
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component XNOR4
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         B:	in	Logic4;
	         C:	in	Logic4;
	         D:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component XNORn
	generic (n:	in	Positive;
	         tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Vector4 (1 to n);
	         Z:	out	Logic4);
    end component;

    component BUF
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component INV
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tW:	in	Time	:= 0ns);	-- min. pulse width
	port    (A:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component DFF
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tSU:	in	Time	:= 0ns;		-- setup time
	         tH:	in	Time	:= 0ns);	-- hold time
	port    (D:	in	Logic4;
	         Clk:	in	Logic4;
	         Clr:	in	Logic4;
	         Set:	in	Logic4;
	         Q:	out	Logic4;
	         QB:	out	Logic4);
    end component;

    component JKFF
	generic (tPLH:	in	Time	:= 0ns;		-- rise prop. delay
	         tPHL:	in	Time	:= 0ns;		-- fall prop. delay
	         tSU:	in	Time	:= 0ns;		-- setup time
	         tH:	in	Time	:= 0ns);	-- hold time
	port    (J:	in	Logic4;
	         K:	in	Logic4;
	         Clk:	in	Logic4;
	         Clr:	in	Logic4;
	         Set:	in	Logic4;
	         Q:	out	Logic4;
	         QB:	out	Logic4);
    end component;

    component LATCH
	port (R:	in	Logic4;
	      S:	in	Logic4;
	      Q:	out	Logic4;
	      QB:	out	Logic4);
    end component;

    component TRIBUF
	port (D:	in	Logic4;
	      En:	in	Logic4;
	      Z:	out	Logic4);
    end component;

    component UXFR			-- unidirectional transfer gate
	port (D:	in	Logic4;
	      En:	in	Logic4;
	      Z:	out	Logic4);
    end component;

    component BXFR			-- bidirectional transfer gate
	port (En:	in	Logic4;
	      D1:	linkage	Logic4;
	      D2:	linkage	Logic4);
    end component;

    component DELAY_LINE
	generic (Delay:	in	Time);
	port    (D:	in	Logic4;
	         Z:	out	Logic4);
    end component;

    component RAM
	generic (AddressBits:	in	Natural;
	         DataBits:	in	Natural);
	port    (En1:		in	Logic4;
	         En2:		in	Logic4;
	         RW:		in	Logic4;	-- R = '0', W = '1'
	         Address:	in	Vector4 (AddressBits-1 downto 0);
	         Data:		inout	Vector4 (DataBits-1    downto 0));
    end component;

    component ROM
	generic (AddressBits:	in	Natural;
	         DataBits:	in	Natural;
	         Contents:	in	Matrix4 (2**AddressBits-1 downto 0,
					         DataBits-1       downto 0));
	port    (En1:		in	Logic4;
	         En2:		in	Logic4;
	         Address:	in	Vector4 (AddressBits-1 downto 0);
	         Data:		out	Vector4 (DataBits-1    downto 0));
    end component;

end Components;