------------------------------------------------------------------------------ -- -- This ENTITIES File was Developed by Honeywell Inc to allow -- Simulation of the VDEG_Portable Components as modified for Logic4 -- Inputs. -- -- -- HISTORY: -- 16-July-89 JW -- Components Pakage converted. Changes Inputs to Logic4 rather -- than Vector4 to allow use with traditional netlisters. -- ------------------------------------------------------------------------------ ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity AND2 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1: in Logic4; Z: out Logic4); end AND2; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity AND3 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2: in Logic4; Z: out Logic4); end AND3; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity AND4 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2,A3: in Logic4; Z: out Logic4); end AND4; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity ANDn is generic (n: Positive; tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A: in Vector4 (1 to n); Z: out Logic4); end ANDn; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity NAND2 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1: in Logic4; Z: out Logic4); end NAND2; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity NAND3 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2: in Logic4; Z: out Logic4); end NAND3; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity NAND4 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2,A3: in Logic4; Z: out Logic4); end NAND4; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity NANDn is generic (n: Positive; tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A: in Vector4 (1 to n); Z: out Logic4); end NANDn; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity OR2 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1: in Logic4; Z: out Logic4); end OR2; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity OR3 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2: in Logic4; Z: out Logic4); end OR3; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity OR4 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2,A3: in Logic4; Z: out Logic4); end OR4; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity ORn is generic (n: Positive; tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A: in Vector4 (1 to n); Z: out Logic4); end ORn; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity NOR2 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1: in Logic4; Z: out Logic4); end NOR2; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity NOR3 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2: in Logic4; Z: out Logic4); end NOR3; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity NOR4 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2,A3: in Logic4; Z: out Logic4); end NOR4; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity NORn is generic (n: Positive; tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A: in Vector4 (1 to n); Z: out Logic4); end NORn; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity XOR2 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1: in Logic4; Z: out Logic4); end XOR2; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity XOR3 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2: in Logic4; Z: out Logic4); end XOR3; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity XOR4 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2,A3: in Logic4; Z: out Logic4); end XOR4; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity XORn is generic (n: Positive; tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A: in Vector4 (1 to n); Z: out Logic4); end XORn; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity XNOR2 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1: in Logic4; Z: out Logic4); end XNOR2; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity XNOR3 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2: in Logic4; Z: out Logic4); end XNOR3; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity XNOR4 is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A0,A1,A2,A3: in Logic4; Z: out Logic4); end XNOR4; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity XNORn is generic (n: Positive; tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A: in Vector4 (1 to n); Z: out Logic4); end XNORn; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity BUF is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A: in Logic4; Z: out Logic4); end BUF; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity INV is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tW: Time := 0ns); -- min. pulse width port (A: in Logic4; Z: out Logic4); end INV; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity DFF is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tSU: Time := 0ns; -- setup time tH: Time := 0ns); -- hold time port (D: in Logic4; Clk: in Logic4; Clr: in Logic4; Set: in Logic4; Q: out Logic4; QB: out Logic4); end DFF; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity JKFF is generic (tPLH: Time := 0ns; -- rise prop. delay tPHL: Time := 0ns; -- fall prop. delay tSU: Time := 0ns; -- setup time tH: Time := 0ns); -- hold time port (J: in Logic4; K: in Logic4; Clr: in Logic4; Set: in Logic4; Q: out Logic4; QB: out Logic4); end JKFF; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity LATCH is port (R: in Logic4; S: in Logic4; Q: out Logic4; QB: out Logic4); end LATCH; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity TRIBUF is port (D: in Logic4; En: in Logic4; Z: out Logic4); end TRIBUF; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity UXFR is -- unidirectional transfer gate port (D: in Logic4; En: in Logic4; Z: out Logic4); end UXFR; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity BXFR is -- bidirectional transfer gate port (En: in Logic4; D1: linkage Logic4; D2: linkage Logic4); end BXFR; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity DELAY_LINE is generic (Delay: Time); port (D: in Logic4; Z: out Logic4); end DELAY_LINE; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity RAM is generic (AddressBits: in Natural; DataBits: in Natural); port (En1: in Logic4; En2: in Logic4; RW: in Logic4; Address: in Vector4 (AddressBits-1 downto 0); Data: inout Vector4 (DataBits-1 downto 0)); end RAM; ------------------------------------------ ------------------------------------------ library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; entity ROM is generic (AddressBits: in Natural; DataBits: in Natural; Contents: in Matrix4 (2**AddressBits-1 downto 0, DataBits-1 downto 0)); port (En1: in Logic4; En2: in Logic4; Address: in Vector4 (AddressBits-1 downto 0); Data: out Vector4 (DataBits-1 downto 0)); end ROM; ------------------------------------------------------------------------------ -- -- This Architectures File was Developed by Honeywell Inc to allow -- Simulation of the VDEG_Portable Components as modified for Logic4 -- Inputs. -- -- History -- 7-89 JW All Combinational componnents coded July 1987. -- No attempt to use the minimum pulse width generic since it is -- unclear at this time what the specific effects will be. -- ------------------------------------------------------------------------------ ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF AND2 is begin process(A0,A1) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := sense(A0,'X') and sense(A1,'X'); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF AND3 is begin process(A0,A1,A2) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := sense(A0,'X') and sense(A1,'X') and sense(A2,'X'); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF AND4 is begin process(A0,A1,A2,A3) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := sense(A0,'X') and sense(A1,'X') and sense(A2,'X') and sense(A3,'X'); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF ANDn is begin process(A) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := A(0); for i in 1 to n - 1 loop new_value := new_value and A(i); end loop; if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF NAND2 is begin process(A0,A1) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := sense(A0,'X') nand sense(A1,'X'); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF NAND3 is begin process(A0,A1,A2) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := not (sense(A0,'X') and sense(A1,'X') and sense(A2,'X')); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF NAND4 is begin process(A0,A1,A2,A3) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := (sense(A0,'X') and sense(A1,'X') and sense(A2,'X') and sense(A3,'X')); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF NANDn is begin process(A) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := A(0); for i in 1 to n - 1 loop new_value := new_value and A(i); end loop; new_value := not (new_value); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF OR2 is begin process(A0,A1) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := sense(A0,'X') or sense(A1,'X'); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF OR3 is begin process(A0,A1,A2) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := (sense(A0,'X') or sense(A1,'X')) or sense(A2,'X'); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF OR4 is begin process(A0,A1,A2,A3) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := (sense(A0,'X') or sense(A1,'X')) or ( sense(A2,'X') or sense(A3,'X')); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF ORn is begin process(A) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := A(0); for i in 1 to n - 1 loop new_value := new_value or A(i); end loop; if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF NOR2 is begin process(A0,A1) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := sense(A0,'X') nor sense(A1,'X'); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF NOR3 is begin process(A0,A1,A2) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := (sense(A0,'X') or sense(A1,'X') or sense(A2,'X')); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF NOR4 is begin process(A0,A1,A2,A3) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := not(sense(A0,'X') or sense(A1,'X') or sense(A2,'X') or sense(A3,'X')); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF NORn is begin process(A) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := A(0); for i in 1 to n - 1 loop new_value := new_value or A(i); end loop; new_value := not(new_value); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF XOR2 is begin process(A0,A1) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := sense(A0,'X') xor sense(A1,'X'); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF XOR3 is begin process(A0,A1,A2) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := sense(A0,'X') xor sense(A1,'X') xor sense(A2,'X'); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF XOR4 is begin process(A0,A1,A2,A3) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := sense(A0,'X') xor sense(A1,'X') xor sense(A2,'X') xor sense(A3,'X'); if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF XORn is begin process(A) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := A(0); for i in 1 to n - 1 loop new_value := new_value xor A(i); end loop; if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF BUF is begin process(A) variable last_value :Logic4; -- needed for selection -- of delay variable tDelay,tLongest :Time; begin if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case A is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= A after tDelay; last_value := A; end process; end VDEG; ------------------------------------------- ------------------------------------------- library VDEG_Portable; use VDEG_Portable.Types.all; use VDEG_Portable.all; ARCHITECTURE VDEG OF INV is begin process(A) variable last_value :Logic4; -- needed for selection -- of delay variable new_value :Logic4; variable tDelay,tLongest :Time; begin new_value := not A; if tPHL > tPLH then tLongest := tPHL; else tLongest := tPLH; end if; case new_value is when '0' => tDelay := tPHL; when '1' => tDelay := tPLH; when others => tDelay := tLongest; end case; Z <= new_value after tDelay; last_value := new_value; end process; end VDEG; --library VDEG_Portable; --use VDEG_Portable.Types.all; --use VDEG_Portable.all; -- -- ARCHITECTURE VDEG OF DFF is -- generic (tPLH: Time := 0ns; -- rise prop. delay -- tPHL: Time := 0ns; -- fall prop. delay -- tSU: Time := 0ns; -- setup time -- tH: Time := 0ns); -- hold time -- port (D: in Logic4; -- Clk: in Logic4; -- Clr: in Logic4; -- Set: in Logic4; -- Q: out Logic4; -- QB: out Logic4); -- end VDEG; -- --library VDEG_Portable; --use VDEG_Portable.Types.all; --use VDEG_Portable.all; -- ARCHITECTURE VDEG OF JKFF is -- generic (tPLH: Time := 0ns; -- rise prop. delay -- tPHL: Time := 0ns; -- fall prop. delay -- tSU: Time := 0ns; -- setup time -- tH: Time := 0ns); -- hold time -- port (J: in Logic4; -- K: in Logic4; -- Clr: in Logic4; -- Set: in Logic4; -- Q: out Logic4; -- QB: out Logic4); -- end VDEG; -- --library VDEG_Portable; --use VDEG_Portable.Types.all; --use VDEG_Portable.all; -- ARCHITECTURE VDEG OF LATCH -- port (R: in Logic4; -- S: in Logic4; -- Q: out Logic4; -- QB: out Logic4); -- end VDEG; -- --library VDEG_Portable; --use VDEG_Portable.Types.all; --use VDEG_Portable.all; -- ARCHITECTURE VDEG OF TRIBUF -- port (D: in Logic4; -- En: in Logic4; -- Z: out Logic4); -- end VDEG; -- --library VDEG_Portable; --use VDEG_Portable.Types.all; --use VDEG_Portable.all; -- ARCHITECTURE VDEG OF UXFR -- unidirectional transfer gate -- port (D: in Logic4; -- En: in Logic4; -- Z: out Logic4); -- end VDEG; -- --library VDEG_Portable; --use VDEG_Portable.Types.all; --use VDEG_Portable.all; -- ARCHITECTURE VDEG OF BXFR -- bidirectional transfer gate -- port (En: in Logic4; -- D1: linkage Logic4; -- D2: linkage Logic4); -- end VDEG; -- --library VDEG_Portable; --use VDEG_Portable.Types.all; --use VDEG_Portable.all; -- ARCHITECTURE VDEG OF DELAY_LINE is -- generic (Delay: Time); -- port (D: in Logic4; -- Z: out Logic4); -- end VDEG; -- --library VDEG_Portable; --use VDEG_Portable.Types.all; --use VDEG_Portable.all; -- -- ARCHITECTURE VDEG OF RAM is -- generic (AddressBits: in Natural; -- DataBits: in Natural); -- port (En1: in Logic4; -- En2: in Logic4; -- RW: in Logic4; -- Address: in Vector4 (AddressBits-1 downto 0); -- Data: inout Vector4 (DataBits-1 downto 0)); -- end VDEG; -- --library VDEG_Portable; --use VDEG_Portable.Types.all; --use VDEG_Portable.all; -- ARCHITECTURE VDEG OF ROM is -- generic (AddressBits: in Natural; -- DataBits: in Natural; -- Contents: in Matrix4 (2**AddressBits-1 downto 0, -- DataBits-1 downto 0)); -- port (En1: in Logic4; -- En2: in Logic4; -- Address: in Vector4 (AddressBits-1 downto 0); -- Data: out Vector4 (DataBits-1 downto 0)); -- end VDEG; --