library vdeg_portable;
use vdeg_portable.types.all;
use work.all;

Package benchmark_function_package is

        -- functions used in the VDEG Benchmark Set

function increment(vector:Vector4) return Vector4;
        -- returns a vector 1 bit wider than the input vector
        
        
function Vector4_to_Natural(vector:Vector4) return natural;
        -- If a vector is composed entirely of '1' and '0' elements
        -- Vector4_to_Natural returns a natural number, else it
        -- returns 0. Used for indexing a functional array.

end benchmark_function_package;

---------------------------------------------------------

library vdeg_portable;
use vdeg_portable.types.all;
use work.all;

Package body benchmark_function_package is

function increment(vector:Vector4) return Vector4 is
	variable temp:Vector4(vector'length downto 0);
	variable cin : Logic4:='1';
begin
	for i in 0 to vector'length-1 loop
		temp(i) := vector(i) xor cin;
		cin     := vector(i) and cin;
	end loop;
        temp(vector'length) := cin;
        return temp;
end increment;




function Vector4_to_Natural(vector:Vector4) return natural is 

	variable num,k : natural;

   begin
	for i in vector'range loop
		
		if Sense(vector(i),'X') = 'X' then 
			assert false
			    report " Indeterminate value in vector conversion"
                            severity warning;
                        num := 0;
			exit;
		elsif Sense(vector(i),'X') = '0' then
		        k := 0;
                elsif Sense(vector(i),'X') = '1' then
                        k := 1;		

		end if;

			num := num + k*(2**i);
	end loop;
	return num;
	end Vector4_to_Natural;

end BENCHMARK_FUNCTION_PACKAGE;



---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------

--          Latch Models -- 1 bit and four bits

---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------


library vdeg_portable;
use vdeg_portable.types.all;
use work.all;

Entity Latch is
    port (Data      : in   Logic4;
          Load      : in   Logic4;
          EnA,EnB   : in   Logic4;
          Abus,Bbus : out  DotX);
end Latch;

-------------------------------------------------------------------

library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Architecture DataFlow of Latch is
    Signal LtcData : Logic4;
begin
    Abus    <= Drive(LtcData) when Sense(EnA,'X')  = '1' else 
               Drive('Z');
    Bbus    <= Drive(LtcData) when Sense(EnB,'X')  = '1' else 
              Drive('Z');
    LtcData <= sense(Data,'X')    when sense(Load,'X') = '1' else
               LtcData;
end DataFlow;

-------------------------------------------
library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Entity Latch4 is
    port (Data      : in   Vector4(3 downto 0);
          Load      : in   Logic4;
          EnA,EnB   : in   Logic4;
          Abus,Bbus : out  BusX(3 downto 0));
end Latch4;

library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Architecture DataFlow of Latch4 is
    Signal LtcData : Vector4(3 downto 0);
begin
    Abus    <= Drive(LtcData) when Sense(EnA,'X')  = '1' else 
              Drive("ZZZZ");
    Bbus    <= Drive(LtcData) when Sense(EnB,'X')  = '1' else 
              Drive("ZZZZ");
    LtcData <= sense(Data,'X')    when sense(Load,'X') = '1' else
               LtcData;
end DataFlow;

------------------------------------------------------------------

library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Architecture Structure of Latch4 is


    Signal LtcData : Vector4(3 downto 0);


Component Latch
    port (Data      : in   Logic4;
          Load      : in   Logic4;
          EnA,EnB   : in   Logic4;
          Abus,Bbus : out  DotX);
    end Component;

-------------  Configuration Section
    
for All:Latch use entity  vdeg_benchmark.Latch(DataFlow);    

begin
               
LT0 :   Latch 
            port map(Data(0),Load,EnA,EnB,Abus(0),Bbus(0));

LT1 :   Latch 
            port map(Data(1),Load,EnA,EnB,Abus(1),Bbus(1));

LT2 :   Latch 
            port map(Data(2),Load,EnA,EnB,Abus(2),Bbus(2));

LT3 :   Latch 
            port map(Data(3),Load,EnA,EnB,Abus(3),Bbus(3));
         
               
end Structure;


----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------

--     Decode Section  

----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------

library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Entity Decode_buffer is
	port (a:in logic4;
	      f:out DotAnd);
end Decode_buffer;


---------------------------------------------------------------

library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Architecture DataFlow of Decode_buffer is

begin

	f <= Drive(Sense(a,'X'));

end DataFlow;


library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;


Entity Decode_buffer4 is
	port (a: in Vector4(3 downto 0);
	      f: out DotAnd);
end Decode_buffer4;


library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Architecture Structure of Decode_buffer4 is

component Decode_buffer
	port (a:in logic4;
	      f:out DotAnd);
end component;

-------------  Configuration Section
    
for All:Decode_buffer use entity  vdeg_benchmark.Decode_buffer(DataFlow);    

begin
               
DB0: Decode_buffer
            port map(a(0),f);
               
DB1: Decode_buffer
            port map(a(1),f);
               
DB2: Decode_buffer
            port map(a(2),f);
               
DB3: Decode_buffer
            port map(a(3),f);

end Structure;

--------------------------------------------------------------

library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;


entity Decode_4_to_16 is
	port(vector :in Vector4(3 downto 0);
	     DecodeLines :out BusAnd(15 downto 0));
end Decode_4_to_16;

----------------------------------------------------------------

library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Architecture Structure of Decode_4_to_16 is

Signal a0,a1,a2,a3 : Logic4;
Signal anot0,anot1,anot2,anot3 : Logic4;

--     The following are required to specify decode attachments
               
Signal Attach_code0 : Vector4(3 downto 0);
Signal Attach_code1 : Vector4(3 downto 0);
Signal Attach_code2 : Vector4(3 downto 0);
Signal Attach_code3 : Vector4(3 downto 0);
Signal Attach_code4 : Vector4(3 downto 0);
Signal Attach_code5 : Vector4(3 downto 0);
Signal Attach_code6 : Vector4(3 downto 0);
Signal Attach_code7 : Vector4(3 downto 0);
Signal Attach_code8 : Vector4(3 downto 0);
Signal Attach_code9 : Vector4(3 downto 0);
Signal Attach_code10 : Vector4(3 downto 0);
Signal Attach_code11 : Vector4(3 downto 0);
Signal Attach_code12 : Vector4(3 downto 0);
Signal Attach_code13 : Vector4(3 downto 0);
Signal Attach_code14 : Vector4(3 downto 0);
Signal Attach_code15 : Vector4(3 downto 0);

-- Signal DecodeLines(15 downto 0) : BusAnd;  

component Decode_buffer4
	port (a:in Vector4(3 downto 0);
	      f:out DotAnd);
end component;

-------------  Configuration Section
    
for All:Decode_buffer4 use entity  vdeg_benchmark.Decode_buffer4(Structure);

begin

a0 <= vector(0);
a1 <= vector(1);
a2 <= vector(2);
a3 <= vector(3);

anot0 <= not vector(0);
anot1 <= not vector(1);
anot2 <= not vector(2);
anot3 <= not vector(3);

--   Bundle lines together
--  The attach code signal is required to create a vector 
--  for input to the decode_buffer4. This cannot be done in
--  the instantiation since "An actual signal associated with 
--  a formal port or signal parameter must be a static name "
               
Attach_code0 <= anot3 & anot2 & anot1 & anot0;
Attach_code1 <= anot3 & anot2 & anot1 & a0;
Attach_code2 <= anot3 & anot2 & a1 & anot0;
Attach_code3 <= anot3 & anot2 & a1 & a0;
Attach_code4 <= anot3 & a2 & anot1 & anot0;
Attach_code5 <= anot3 & a2 & anot1 & a0;
Attach_code6 <= anot3 & a2 & a1 & anot0;
Attach_code7 <= anot3 & a2 & a1 & a0;
Attach_code8 <= a3 & anot2 & anot1 & anot0;
Attach_code9 <= a3 & anot2 & anot1 & a0;
Attach_code10 <= a3 & anot2 & a1 & anot0;
Attach_code11 <= a3 & anot2 & a1 & a0;
Attach_code12 <= a3 & a2 & anot1 & anot0;
Attach_code13 <= a3 & a2 & anot1 & a0;
Attach_code14 <= a3 & a2 & a1 & anot0;
Attach_code15 <= a3 & a2 & a1 & a0;
               
DB0: Decode_buffer4 port map( Attach_code0,DecodeLines(0));
DB1: Decode_buffer4 port map( Attach_code1,DecodeLines(1));
DB2: Decode_buffer4 port map( Attach_code2,DecodeLines(2));
DB3: Decode_buffer4 port map( Attach_code3,DecodeLines(3));
DB4: Decode_buffer4 port map( Attach_code4,DecodeLines(4));
DB5: Decode_buffer4 port map( Attach_code5,DecodeLines(5));
DB6: Decode_buffer4 port map( Attach_code6,DecodeLines(6));
DB7: Decode_buffer4 port map( Attach_code7,DecodeLines(7));
DB8: Decode_buffer4 port map (Attach_code8,DecodeLines(8));
DB9: Decode_buffer4 port map (Attach_code9,DecodeLines(9));
DB10: Decode_buffer4 port map (Attach_code10,DecodeLines(10));
DB11: Decode_buffer4 port map (Attach_code11,DecodeLines(11));
DB12: Decode_buffer4 port map (Attach_code12,DecodeLines(12));
DB13: Decode_buffer4 port map (Attach_code13,DecodeLines(13));
DB14: Decode_buffer4 port map (Attach_code14,DecodeLines(14));
DB15: Decode_buffer4 port map (Attach_code15,DecodeLines(15));

end Structure;


--------------------------------------------------------------
--------------------------------------------------------------
--------------------------------------------------------------

--      Register File (Data Flow and Structure)

--------------------------------------------------------------
--------------------------------------------------------------
--------------------------------------------------------------

library vdeg_portable;
use vdeg_portable.types.all;
use work.all;

Entity Reg_File is
    port (A_Address,B_Address,B_Data : in   Vector4(3 downto 0);
          Clock,RFile_Enable         : in   Logic4;
          Abus,Bbus                  : out  Vector4(3 downto 0));
end Reg_File;

----------------------------------------------------------------
library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Architecture DataFlow of Reg_File is

    Type RamArray is array(natural range 15 downto 0) of Vector4(3 downto 0); 

    Signal Word               : RamArray;
    Signal Ram_Data_In        :Vector4(3 downto 0);
    Signal Write_Enable       : Logic4;
    Signal A_Select,B_Select  : Natural;
begin

        -- The Register File is made of a master Data Latch (Ram_Data_In)
        -- and a Slave Ram
        
-- Load the Master Latch when CLock is low

        Ram_Data_In <= B_Data when Clock = '0' else
                       Ram_Data_In;
                       
-- Write Pulse Control

        Write_Enable <= Clock and RFile_Enable;

-- Convert (decode) Addresses

        A_Select <= Vector4_to_Natural(A_Address);
        B_Select <= Vector4_to_Natural(B_Address);


-- Write to the word selected by the B_Address;
        
        Word(B_Select) <= Ram_Data_In when Write_Enable = '1' else
                          Word(B_Select);

-- Read the A and B addresses
    
        Abus <= Word(A_Select);
        Bbus <= Word(B_Select);

end DataFlow;

------------------------------------------------------------------

library vdeg_portable, vdeg_benchmark;
use vdeg_portable.types.all;
use vdeg_benchmark.benchmark_function_package.all;
use work.all;

Architecture Structure of Reg_File is


    Signal StrbN1, Strb2, StrbN3, Strb4 : Logic4;

    Signal WE,ASel,BSel :Vector4(15 downto 0);
    Signal BSelect : BusX(15 downto 0);
    Signal DecodeAOut, DecodeBOut: BusAnd(15 downto 0);
    Signal Strobe,StrobeBar   : Logic4;
    Signal Ram_Data_In        : Vector4(3 downto 0);
    Signal  MstrOut           : BusX(3 downto 0);
    Signal Write_Enable       : Logic4;
    Signal Bus_A,Bus_B	      : BusX(3 downto 0);
    Signal TiedHi	      : Logic4 := '1';
	Constant Logic1	:Logic4 := '1';

component  INV
    generic (tPLH:  Time    := 0ns;         -- rise prop. delay
             tPHL:  Time    := 0ns;         -- fall prop. delay
             tW:    Time    := 0ns);        -- min. pulse width
    port    (A: in  Logic4;
             Z: out Logic4);
    end component;

component  BUF
    generic (tPLH:  Time    := 0ns;         -- rise prop. delay
             tPHL:  Time    := 0ns;         -- fall prop. delay
             tW:    Time    := 0ns);        -- min. pulse width
    port    (A: in  Logic4;
             Z: out Logic4);
    end component;
    
component Latch4 
    port (Data      : in   Vector4(3 downto 0);
          Load      : in   Logic4;
          EnA,EnB   : in   Logic4;
          Abus,Bbus : out  BusX(3 downto 0));
end component;

Component Decode_4_to_16 
	port(vector :in Vector4(3 downto 0);
	     DecodeLines :out BusAnd(15 downto 0));
end component;

component  AND3
    generic (tPLH:  Time    := 0ns;         -- rise prop. delay
             tPHL:  Time    := 0ns;         -- fall prop. delay
             tW:    Time    := 0ns);        -- min. pulse width
    port    (A0,A1,A2: in  Logic4;
             Z: out Logic4);
    end component;

for all: INV use entity vdeg_portable.inv(vdeg);
for all: BUF use entity vdeg_portable.buf(vdeg);
for all: AND3 use entity vdeg_portable.and3(vdeg);
for all: LATCH4 use entity vdeg_benchmark.latch4(structure);
for all: Decode_4_to_16 use entity vdeg_benchmark.Decode_4_to_16(structure);

begin

TiedHi <= Logic1;

	-- INV is used to setup Strobe and StrobeBar

INV0:  INV
    port map    (Clock,StrobeBar);

INV1:  INV
    port map    (StrobeBar,Strobe);



        -- The Register File is made of a master Data Latch (Ram_Data_In)
        -- and a Slave Ram 
        -- The master Latch is identical to the individual slave latches
        -- but is strobed by the opposite phase of the clock. The A and B
        -- outputs are always enabled and are tied together to 
        -- provide the extra drive for the Ram_Data_In Lines. 
        
        -- (Tests opperation of BusX for identical data)

        
MSTLTC: Latch4 
    port map( B_Data,StrobeBar , TiedHi, TiedHi, MstrOut, MstrOut);

-- Convert type of MstrOut

	Ram_Data_In <= Vector4(MstrOut);
        
        -- The Slave Ram is an array of four bit latches. 
        -- The Write Enable is functionally the And of Strobe
        -- And RFile_Enable. This is delayed to allow the 
        -- Array to Settle at the correct B address.
        
RMLTC0: Latch4 
    port map( Ram_Data_In, WE(0),
              ASel(0), BSel(0),
              Bus_A, Bus_B);  
                              
RMLTC1: Latch4 
    port map( Ram_Data_In, WE(1),
              ASel(1), BSel(1),
              Bus_A, Bus_B);  
                              
RMLTC2: Latch4 
    port map( Ram_Data_In, WE(2),
              ASel(2), BSel(2),
              Bus_A, Bus_B);  
                              
RMLTC3: Latch4 
    port map( Ram_Data_In, WE(3),
              ASel(3), BSel(3),
              Bus_A, Bus_B);  
                              
RMLTC4: Latch4 
    port map( Ram_Data_In, WE(4),
              ASel(4), BSel(4),
              Bus_A, Bus_B);  
                              
RMLTC5: Latch4 
    port map( Ram_Data_In, WE(5),
              ASel(5), BSel(5),
              Bus_A, Bus_B);  
                              
RMLTC6: Latch4 
    port map( Ram_Data_In, WE(6),
              ASel(6), BSel(6),
              Bus_A, Bus_B);  
                              
RMLTC7: Latch4 
    port map( Ram_Data_In, WE(7),
              ASel(7), BSel(7),
              Bus_A, Bus_B);  
                              
RMLTC8: Latch4 
    port map( Ram_Data_In, WE(8),
              ASel(8), BSel(8),
              Bus_A, Bus_B);  
                              
RMLTC9: Latch4 
    port map( Ram_Data_In, WE(9),
              ASel(9), BSel(9),
              Bus_A, Bus_B);  
                              
RMLTC10: Latch4 
    port map( Ram_Data_In, WE(10),
              ASel(10), BSel(10),
              Bus_A, Bus_B);  
                              
RMLTC11: Latch4 
    port map( Ram_Data_In, WE(11),
              ASel(11), BSel(11),
              Bus_A, Bus_B);  
                              
RMLTC12: Latch4 
    port map( Ram_Data_In, WE(12),
              ASel(12), BSel(12),
              Bus_A, Bus_B);  
                              
RMLTC13: Latch4 
    port map( Ram_Data_In, WE(13),
              ASel(13), BSel(13),
              Bus_A, Bus_B);  
                              
RMLTC14: Latch4 
    port map( Ram_Data_In, WE(14),
              ASel(14), BSel(14),
              Bus_A, Bus_B);  
                              
RMLTC15: Latch4 
    port map( Ram_Data_In, WE(15),
              ASel(15), BSel(15),
              Bus_A, Bus_B);  

    -- The A select lines are totally asynchronous in nature since
    -- they simply enable mory output selectors.                              

DecodeA: Decode_4_to_16 
	port map( A_Address, DecodeAOut);

	Asel <= Vector4(DecodeAOut);    --  Required for type conversion

DecodeB: Decode_4_to_16 
	port map( B_Address, DecodeBOut);

	Bsel <= Vector4(DecodeBOut);    --  Required for type conversion
	                                

    -- The B select lines are latched during write to guard against
    -- spurious noise and unintentional writes.  The B select latch
    -- is made of four four bit latches and loads in synchrony with
    -- the slave latches, locking out changes to the B address during
    -- the Write Cycle. The read address, Like the A select address is 
    -- Asynchronous;

BADDLTC0: Latch4 
    port map(Bsel(3 downto 0), Strobe,
             TiedHi,TiedHi,
             Bselect(3 downto 0), BSelect(3 downto 0));  

BADDLTC1: Latch4 
    port map(Bsel(7 downto 4), Strobe, TiedHi, TiedHi,
		 Bselect(7 downto 4), BSelect(7 downto 4));  

BADDLTC2: Latch4 
    port map(Bsel(11 downto 8), Strobe, TiedHi, TiedHi,
		 Bselect(11 downto 8), BSelect(11 downto 8));  

BADDLTC3: Latch4 
    port map(Bsel(15 downto 12), Strobe, TiedHi, TiedHi,
		 Bselect(15 downto 12), BSelect(15 downto 12));  

-- Write Pulse Control. To Ensure that a write enable is sent only after
-- a byte selection has been made and is stable, the write enable is 
-- generated from the Bselect line, Strobe and a delayed version of strobe.


StrbDly1:  INV
    port map    ( Strobe, StrbN1);

StrbDly2:  INV
    port map    ( StrbN1, Strb2);

StrbDly3:  INV
    port map    ( Strb2, StrbN3);

StrbDly4:  INV
    port map    ( StrbN3, Strb4);
    

Wenbl0:     AND3
    port map    (Strobe,Strb4,BSelect(0), WE(0));
 
Wenbl1:     AND3
    port map    (Strobe,Strb4,BSelect(1), WE(1));
 
Wenbl2:     AND3
    port map    (Strobe,Strb4,BSelect(2), WE(2));
 
Wenbl3:     AND3
    port map    (Strobe,Strb4,BSelect(3), WE(3));
 
Wenbl4:     AND3
    port map    (Strobe,Strb4,BSelect(4), WE(4));
 
Wenbl5:     AND3
    port map    (Strobe,Strb4,BSelect(5), WE(5));
 
Wenbl6:     AND3
    port map    (Strobe,Strb4,BSelect(6), WE(6));
 
Wenbl7:     AND3
    port map    (Strobe,Strb4,BSelect(7), WE(7));
 
Wenbl8:     AND3
    port map    (Strobe,Strb4,BSelect(8), WE(8));
 
Wenbl9:     AND3
    port map    (Strobe,Strb4,BSelect(9), WE(9));
 
Wenbl10:     AND3
    port map    (Strobe,Strb4,BSelect(10), WE(10));
 
Wenbl11:     AND3
    port map    (Strobe,Strb4,BSelect(11), WE(11));
 
Wenbl12:     AND3
    port map    (Strobe,Strb4,BSelect(12), WE(12));
 
Wenbl13:     AND3
    port map    (Strobe,Strb4,BSelect(13), WE(13));
 
Wenbl14:     AND3
    port map    (Strobe,Strb4,BSelect(14), WE(14));
 
Wenbl15:     AND3
    port map    (Strobe,Strb4,BSelect(15), WE(15));

OutBufA0:     BUF 
    port map   (Bus_A(0),Abus(0));

OutBufA1:     BUF 
    port map   (Bus_A(1),Abus(1));

OutBufA2:     BUF 
    port map   (Bus_A(2),Abus(2));

OutBufA3:     BUF 
    port map   (Bus_A(3),Abus(3));

OutBufB0:     BUF 
    port map   (Bus_B(0),Bbus(0));

OutBufB1:     BUF 
    port map   (Bus_B(1),Bbus(1));

OutBufB2:     BUF 
    port map   (Bus_B(2),Bbus(2));

OutBufB3:     BUF 
    port map   (Bus_B(3),Bbus(3));

end Structure;