7/22/89  From John Winkler
              Honeywell,SSEC
              12001 St. Highway 55
              Plymouth MN. 55441
              JWINKLER@CIM-VAX.HONEYWELL.COM
              
A FIRST CUT AT VDEG PACKAGE VALIDATION CODE....

Validation Code exists in Five files:

1)  New_Entities.VHD
    Entities and Architectures for Basic Components. The 
    formal_port_clause(s) have been changed to connect to individual bits 
    of type Logic4. These entities will not match package Components.

2)  BasicTests.VHD
    Contains tests for Dot And Bus types.

3)  RFILE_benchmark.VHD
    Contains:
        Package benchmark_function_package
    *** Entity Latch  (DataFlow architecture)
    *** Entity Latch4 (DataFlow and Structure architectures)
        Entity Decode_buffer (DataFlow architecture)
        Decode_buffer4 (Structure architecture)
        entity Decode_4_to_16(Structure architecture)
    +++ Entity Reg_File(DataFlow and Structure architectures)

4)  Benchmark_Benches.VHD
    Contains Test benches for the Register File and Decode_4_to_16



    Analyse these Files in ascending order.

    *** The Latch files have been analysed but not simulated
    +++ The Dataflow Architecture Has been Simulated but the
        Structure has only been analyzed.