-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\COUNT0.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\COUNT0.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP6.$$$ 
-- Version V2.1.4
-- Definition of  COUNT0
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Wed Mar  1 19:49:44 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity COUNT0 is
   port (
      CLOCK : in std_logic ;
      COUNT_OUT_7, COUNT_OUT_6, COUNT_OUT_5, COUNT_OUT_4, COUNT_OUT_3, 
      COUNT_OUT_2, COUNT_OUT_1, COUNT_OUT_0 : inout std_logic := '0') ;
end COUNT0 ;

architecture exemplar of COUNT0 is
   signal
      vh_9, vh_10, vh_11, vh_12, vh_15, vh_16, vh_19, vh_22, vh_23, vh_26, 
      vh_29, vh_30, vh_33, vh_36: std_logic ;
 
begin
   g1000 : AND3I0 port map ( Q=>vh_9, A=>COUNT_OUT_2, B=>COUNT_OUT_1, C=>COUNT_OUT_0);
   g1001 : AND3I0 port map ( Q=>vh_10, A=>COUNT_OUT_4, B=>COUNT_OUT_3, C=>vh_9);
   g1002 : AND3I0 port map ( Q=>vh_11, A=>COUNT_OUT_6, B=>COUNT_OUT_5, C=>vh_10);
   g1003 : MUX2X2 port map ( Q=>vh_12, A=>vh_11, B=>vh_11, S=>COUNT_OUT_7);
   g1004 : AND2I0 port map ( Q=>vh_15, A=>COUNT_OUT_5, B=>vh_10);
   g1005 : MUX2X2 port map ( Q=>vh_16, A=>vh_15, B=>vh_15, S=>COUNT_OUT_6);
   g1006 : MUX2X2 port map ( Q=>vh_19, A=>vh_10, B=>vh_10, S=>COUNT_OUT_5);
   g1007 : AND2I0 port map ( Q=>vh_22, A=>COUNT_OUT_3, B=>vh_9);
   g1008 : MUX2X2 port map ( Q=>vh_23, A=>vh_22, B=>vh_22, S=>COUNT_OUT_4);
   g1009 : MUX2X2 port map ( Q=>vh_26, A=>vh_9, B=>vh_9, S=>COUNT_OUT_3);
   g1010 : AND2I0 port map ( Q=>vh_29, A=>COUNT_OUT_1, B=>COUNT_OUT_0);
   g1011 : MUX2X2 port map ( Q=>vh_30, A=>vh_29, B=>vh_29, S=>COUNT_OUT_2);
   g1012 : MUX2X2 port map ( Q=>vh_33, A=>COUNT_OUT_1, B=>COUNT_OUT_1, S=>COUNT_OUT_0);
   g1013 : INV port map ( Q=>vh_36, A=>COUNT_OUT_0);
   vh_38 : DFF port map ( CLK=>CLOCK, D=>vh_12, Q=>COUNT_OUT_7);
   vh_39 : DFF port map ( CLK=>CLOCK, D=>vh_16, Q=>COUNT_OUT_6);
   vh_40 : DFF port map ( CLK=>CLOCK, D=>vh_19, Q=>COUNT_OUT_5);
   vh_41 : DFF port map ( CLK=>CLOCK, D=>vh_23, Q=>COUNT_OUT_4);
   vh_42 : DFF port map ( CLK=>CLOCK, D=>vh_26, Q=>COUNT_OUT_3);
   vh_43 : DFF port map ( CLK=>CLOCK, D=>vh_30, Q=>COUNT_OUT_2);
   vh_44 : DFF port map ( CLK=>CLOCK, D=>vh_33, Q=>COUNT_OUT_1);
   vh_45 : DFF port map ( CLK=>CLOCK, D=>vh_36, Q=>COUNT_OUT_0);

end exemplar ;