-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\COUNT1.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\COUNT1.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP18.$$$ 
-- Version V2.1.4
-- Definition of  COUNT1
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Wed Mar  1 05:58:23 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity COUNT1 is
   port (
      CLOCK, RESET : in std_logic ;
      COUNT_OUT_7, COUNT_OUT_6, COUNT_OUT_5, COUNT_OUT_4, COUNT_OUT_3, 
      COUNT_OUT_2, COUNT_OUT_1, COUNT_OUT_0 : inout std_logic) ;
end COUNT1 ;

architecture exemplar of COUNT1 is
   signal
      vh_10, vh_11, vh_12, vh_13, vh_17, vh_18, vh_22, vh_26, vh_27, vh_31, 
      vh_35, vh_36, vh_40, vh_44: std_logic ;
 
begin
   g1000 : AND3I0 port map ( Q=>vh_10, A=>COUNT_OUT_2, B=>COUNT_OUT_1, C=>COUNT_OUT_0);
   g1001 : AND3I0 port map ( Q=>vh_11, A=>COUNT_OUT_4, B=>COUNT_OUT_3, C=>vh_10);
   g1002 : AND3I0 port map ( Q=>vh_12, A=>COUNT_OUT_6, B=>COUNT_OUT_5, C=>vh_11);
   g1003 : MUX2X2 port map ( Q=>vh_13, A=>vh_12, B=>vh_12, S=>COUNT_OUT_7);
   g1004 : AND2I0 port map ( Q=>vh_17, A=>COUNT_OUT_5, B=>vh_11);
   g1005 : MUX2X2 port map ( Q=>vh_18, A=>vh_17, B=>vh_17, S=>COUNT_OUT_6);
   g1006 : MUX2X2 port map ( Q=>vh_22, A=>vh_11, B=>vh_11, S=>COUNT_OUT_5);
   g1007 : AND2I0 port map ( Q=>vh_26, A=>COUNT_OUT_3, B=>vh_10);
   g1008 : MUX2X2 port map ( Q=>vh_27, A=>vh_26, B=>vh_26, S=>COUNT_OUT_4);
   g1009 : MUX2X2 port map ( Q=>vh_31, A=>vh_10, B=>vh_10, S=>COUNT_OUT_3);
   g1010 : AND2I0 port map ( Q=>vh_35, A=>COUNT_OUT_1, B=>COUNT_OUT_0);
   g1011 : MUX2X2 port map ( Q=>vh_36, A=>vh_35, B=>vh_35, S=>COUNT_OUT_2);
   g1012 : MUX2X2 port map ( Q=>vh_40, A=>COUNT_OUT_1, B=>COUNT_OUT_1, S=>COUNT_OUT_0);
   g1013 : INV port map ( Q=>vh_44, A=>COUNT_OUT_0);
   vh_46 : DFFC port map ( CLK=>CLOCK, CLR=>RESET, D=>vh_13, Q=>COUNT_OUT_7   );
   vh_47 : DFFC port map ( CLK=>CLOCK, CLR=>RESET, D=>vh_18, Q=>COUNT_OUT_6   );
   vh_48 : DFFC port map ( CLK=>CLOCK, CLR=>RESET, D=>vh_22, Q=>COUNT_OUT_5   );
   vh_49 : DFFC port map ( CLK=>CLOCK, CLR=>RESET, D=>vh_27, Q=>COUNT_OUT_4   );
   vh_50 : DFFC port map ( CLK=>CLOCK, CLR=>RESET, D=>vh_31, Q=>COUNT_OUT_3   );
   vh_51 : DFFC port map ( CLK=>CLOCK, CLR=>RESET, D=>vh_36, Q=>COUNT_OUT_2   );
   vh_52 : DFFC port map ( CLK=>CLOCK, CLR=>RESET, D=>vh_40, Q=>COUNT_OUT_1   );
   vh_53 : DFFC port map ( CLK=>CLOCK, CLR=>RESET, D=>vh_44, Q=>COUNT_OUT_0   );

end exemplar ;