-- -- Program -- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\COUNT4.VHD D:\EXEMPLAR\TUTO -- RIAL\HARDWARE\COUNT4.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP16.$$$ -- Version V2.1.4 -- Definition of COUNT4 -- -- VHDL Structural Description, created by -- Exemplar Logic's CORE -- Thu Mar 2 20:08:39 1995 -- -- -- library ieee ; use ieee.std_logic_1164.all ; LIBRARY exemplar; USE exemplar.Cypress_pASIC.ALL; entity COUNT4 is port ( CLOCK, PRESET, CLEAR, PRELOAD, COUNT_IN_3, COUNT_IN_2, COUNT_IN_1, COUNT_IN_0 : in std_logic ; COUNT_OUT_3, COUNT_OUT_2, COUNT_OUT_1, COUNT_OUT_0 : inout std_logic ) ; end COUNT4 ; architecture exemplar of COUNT4 is signal vh_0, vh_1, vh_2, vh_5, vh_6, vh_7, vh_8, vh_10, vh_11, vh_12, vh_13, vh_14, vh_15, vh_16, vh_17, vh_18, vh_19, vh_20, vh_21, vh_22, vh_23, vh_24, vh_25, vh_26, vh_27, vh_28, vh_29, vh_30, vh_31, vh_32, vh_33, vh_34, vh_35, vh_36, vh_38, vh_39, vh_42, vh_43, vh_45, vh_46, vh_47, vh_48, vh_49, vh_51, vh_52, vh_55, vh_56, vh_58, vh_59, vh_60, vh_61, vh_62, vh_64, vh_65, vh_68, vh_69, vh_71, vh_72, vh_73, vh_74, vh_75, vh_77, vh_78, vh_81, vh_83, vh_85: std_logic ; begin g1000 : AND3I2 port map ( Q=>vh_5, A=>PRELOAD, B=>CLEAR, C=>PRESET); g1001 : OR3I0 port map ( Q=>vh_6, A=>CLEAR, B=>vh_5, C=>PRESET); g1002 : AND4I2 port map ( Q=>vh_7, A=>PRELOAD, B=>COUNT_IN_3, C=>CLEAR, D=>PRESET); g1003 : AND3I2 port map ( Q=>vh_8, A=>vh_6, B=>vh_7, C=>PRESET); g1004 : AND2I0 port map ( Q=>vh_10, A=>COUNT_OUT_1, B=>COUNT_OUT_0); g1005 : AND3I0 port map ( Q=>vh_11, A=>vh_10, B=>COUNT_OUT_3, C=>COUNT_OUT_2); g1006 : AND4I3 port map ( Q=>vh_12, A=>COUNT_OUT_3, B=>COUNT_OUT_1, C=>COUNT_OUT_0, D=>COUNT_OUT_2); g1007 : AND2I2 port map ( Q=>vh_13, A=>vh_11, B=>vh_12); g1008 : AND4I3 port map ( Q=>vh_14, A=>COUNT_OUT_0, B=>COUNT_OUT_3, C=>COUNT_OUT_2, D=>COUNT_OUT_1); g1009 : AND4I3 port map ( Q=>vh_15, A=>COUNT_OUT_1, B=>COUNT_OUT_3, C=>COUNT_OUT_2, D=>COUNT_OUT_0); g1010 : AND4I2 port map ( Q=>vh_16, A=>COUNT_OUT_3, B=>COUNT_OUT_0, C=>COUNT_OUT_1, D=>COUNT_OUT_2); g1011 : AND3I3 port map ( Q=>vh_17, A=>vh_14, B=>vh_15, C=>vh_16); g1012 : AND4I2 port map ( Q=>vh_18, A=>COUNT_OUT_3, B=>COUNT_OUT_2, C=>COUNT_OUT_0, D=>COUNT_OUT_1); g1013 : AND4I2 port map ( Q=>vh_19, A=>COUNT_OUT_3, B=>COUNT_OUT_1, C=>COUNT_OUT_0, D=>COUNT_OUT_2); g1014 : AND2I2 port map ( Q=>vh_20, A=>vh_18, B=>vh_19); g1015 : AND3I2 port map ( Q=>vh_21, A=>vh_20, B=>vh_11, C=>vh_12); g1016 : XOR2I0 port map ( Q=>vh_22, A=>COUNT_OUT_1, B=>COUNT_OUT_0); g1017 : AND3I3 port map ( Q=>vh_23, A=>vh_22, B=>COUNT_OUT_3, C=>COUNT_OUT_2); g1018 : AND4I1 port map ( Q=>vh_24, A=>vh_85, B=>COUNT_OUT_0, C=>COUNT_OUT_3, D=>COUNT_OUT_2); g1019 : AND2I2 port map ( Q=>vh_25, A=>vh_23, B=>vh_24); g1020 : XNOR2I0 port map ( Q=>vh_26, A=>COUNT_OUT_0, B=>vh_85); g1021 : AND3I1 port map ( Q=>vh_27, A=>COUNT_OUT_2, B=>COUNT_OUT_3, C=>vh_26); g1022 : AND3I2 port map ( Q=>vh_28, A=>vh_83, B=>vh_22, C=>vh_81); g1023 : AND3I2 port map ( Q=>vh_29, A=>vh_83, B=>vh_26, C=>vh_81); g1024 : AND6I3 port map ( Q=>vh_30, A=>vh_17, B=>vh_21, C=>vh_25, D=>vh_27, E=>vh_28, F=>vh_29); g1025 : OR2I2 port map ( Q=>vh_31, A=>vh_81, B=>vh_30); g1026 : AND4I2 port map ( Q=>vh_32, A=>vh_81, B=>vh_83, C=>COUNT_OUT_0, D=>vh_85); g1027 : AND4I2 port map ( Q=>vh_33, A=>vh_83, B=>vh_85, C=>COUNT_OUT_0, D=>vh_81); g1028 : AND4I2 port map ( Q=>vh_34, A=>vh_85, B=>COUNT_OUT_0, C=>vh_83, D=>vh_81); g1029 : AND6I3 port map ( Q=>vh_35, A=>vh_13, B=>vh_31, C=>vh_17, D=>vh_32, E=>vh_33, F=>vh_34); g1030 : INV port map ( Q=>vh_36, A=>vh_35); g1031 : AND2I2 port map ( Q=>vh_38, A=>vh_7, B=>PRESET); g1032 : AND2I1 port map ( Q=>vh_39, A=>vh_6, B=>vh_38); g1033 : AND4I2 port map ( Q=>vh_42, A=>PRELOAD, B=>COUNT_IN_2, C=>CLEAR, D=>PRESET); g1034 : AND3I2 port map ( Q=>vh_43, A=>vh_6, B=>vh_42, C=>PRESET); g1035 : OR3I1 port map ( Q=>vh_45, A=>vh_85, B=>vh_83, C=>vh_81); g1036 : AND2I0 port map ( Q=>vh_46, A=>vh_83, B=>vh_30); g1037 : AND4I1 port map ( Q=>vh_47, A=>vh_81, B=>vh_83, C=>vh_85, D=>COUNT_OUT_0); g1038 : AND5I3 port map ( Q=>vh_48, A=>vh_45, B=>vh_25, C=>vh_46, D=>vh_29, E=>vh_47); g1039 : INV port map ( Q=>vh_49, A=>vh_48); g1040 : AND2I2 port map ( Q=>vh_51, A=>vh_42, B=>PRESET); g1041 : AND2I1 port map ( Q=>vh_52, A=>vh_6, B=>vh_51); g1042 : AND4I2 port map ( Q=>vh_55, A=>PRELOAD, B=>COUNT_IN_1, C=>CLEAR, D=>PRESET); g1043 : AND3I2 port map ( Q=>vh_56, A=>vh_6, B=>vh_55, C=>PRESET); g1044 : OR3I0 port map ( Q=>vh_58, A=>vh_22, B=>vh_81, C=>vh_83); g1045 : AND2I0 port map ( Q=>vh_59, A=>vh_85, B=>vh_30); g1046 : AND4I3 port map ( Q=>vh_60, A=>vh_83, B=>vh_85, C=>COUNT_OUT_0, D=>vh_81); g1047 : AND5I3 port map ( Q=>vh_61, A=>vh_58, B=>vh_17, C=>vh_59, D=>vh_27, E=>vh_60); g1048 : INV port map ( Q=>vh_62, A=>vh_61); g1049 : AND2I2 port map ( Q=>vh_64, A=>vh_55, B=>PRESET); g1050 : AND2I1 port map ( Q=>vh_65, A=>vh_6, B=>vh_64); g1051 : AND4I2 port map ( Q=>vh_68, A=>PRELOAD, B=>COUNT_IN_0, C=>CLEAR, D=>PRESET); g1052 : AND3I2 port map ( Q=>vh_69, A=>vh_6, B=>vh_68, C=>PRESET); g1053 : AND2I0 port map ( Q=>vh_71, A=>COUNT_OUT_0, B=>vh_30); g1054 : AND2I2 port map ( Q=>vh_72, A=>vh_29, B=>vh_27); g1055 : AND2I2 port map ( Q=>vh_73, A=>vh_15, B=>vh_16); g1056 : AND2I0 port map ( Q=>vh_74, A=>vh_73, B=>vh_20); g1057 : OR3I2 port map ( Q=>vh_75, A=>vh_71, B=>vh_72, C=>vh_74); g1058 : AND2I2 port map ( Q=>vh_77, A=>vh_68, B=>PRESET); g1059 : AND2I1 port map ( Q=>vh_78, A=>vh_6, B=>vh_77); g1060 : BUFF port map ( Q=>COUNT_OUT_3, A=>vh_0); g1061 : BUFF port map ( Q=>vh_81, A=>vh_0); g1062 : BUFF port map ( Q=>COUNT_OUT_2, A=>vh_1); g1063 : BUFF port map ( Q=>vh_83, A=>vh_1); g1064 : BUFF port map ( Q=>COUNT_OUT_1, A=>vh_2); g1065 : BUFF port map ( Q=>vh_85, A=>vh_2); vh_86 : DFFPC port map ( CLK=>CLOCK, CLR=>vh_8, D=>vh_36, PRE=>vh_39, Q=>vh_0); vh_87 : DFFPC port map ( CLK=>CLOCK, CLR=>vh_43, D=>vh_49, PRE=>vh_52, Q=>vh_1); vh_88 : DFFPC port map ( CLK=>CLOCK, CLR=>vh_56, D=>vh_62, PRE=>vh_65, Q=>vh_2); vh_89 : DFFPC port map ( CLK=>CLOCK, CLR=>vh_69, D=>vh_75, PRE=>vh_78, Q=>COUNT_OUT_0); end exemplar ;