-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\COUNT7.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\COUNT7.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP13.$$$ 
-- Version V2.1.4
-- Definition of  COUNT7
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Fri Mar  3 17:22:18 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity COUNT7 is
   port (
      CLOCK, RESET : in std_logic ;
      DIVIDE_OUT : out std_logic) ;
end COUNT7 ;

architecture exemplar of COUNT7 is
   signal
      COUNT_3, COUNT_2, COUNT_1, COUNT_0, vh_2, vh_3, vh_4, vh_5, vh_8, vh_9, 
      vh_10, vh_11, vh_14, vh_15, vh_18: std_logic ;
 
begin
   g1000 : AND3I3 port map ( Q=>vh_2, A=>COUNT_2, B=>COUNT_1, C=>COUNT_0);
   g1001 : AND2I1 port map ( Q=>vh_3, A=>vh_2, B=>COUNT_3);
   g1002 : AND3I2 port map ( Q=>vh_4, A=>COUNT_3, B=>vh_2, C=>RESET);
   g1003 : OR2I0 port map ( Q=>vh_5, A=>vh_3, B=>vh_4);
   g1004 : AND2I2 port map ( Q=>vh_8, A=>COUNT_1, B=>COUNT_0);
   g1005 : MUX2X2 port map ( Q=>vh_9, A=>vh_8, B=>vh_8, S=>COUNT_2);
   g1006 : AND2I1 port map ( Q=>vh_10, A=>vh_9, B=>RESET);
   g1007 : OR2I0 port map ( Q=>vh_11, A=>vh_3, B=>vh_10);
   g1008 : MUX2X1 port map ( Q=>vh_14, A=>COUNT_1, B=>COUNT_1, S=>COUNT_0);
   g1009 : AND3I2 port map ( Q=>vh_15, A=>vh_14, B=>vh_3, C=>RESET);
   g1010 : AND3I3 port map ( Q=>vh_18, A=>vh_3, B=>COUNT_0, C=>RESET);
   vh_22 : DFF port map ( CLK=>CLOCK, D=>vh_5, Q=>COUNT_3);
   vh_23 : DFF port map ( CLK=>CLOCK, D=>vh_11, Q=>COUNT_2);
   vh_24 : DFF port map ( CLK=>CLOCK, D=>vh_15, Q=>COUNT_1);
   vh_25 : DFF port map ( CLK=>CLOCK, D=>vh_18, Q=>COUNT_0);
   vh_26 : DFF port map ( CLK=>CLOCK, D=>vh_3, Q=>DIVIDE_OUT);

end exemplar ;