-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC0.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\LOGIC0.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP14.$$$ 
-- Version V2.1.4
-- Definition of  LOGIC0
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Fri Mar  3 17:42:45 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity LOGIC0 is
   port (
      A_3, A_2, A_1, A_0, B_3, B_2, B_1, B_0, C_3, C_2, C_1, C_0 : in 
      std_logic ;
      Z_3, Z_2, Z_1, Z_0 : out std_logic) ;
end LOGIC0 ;

architecture exemplar of LOGIC0 is
   signal
      vh_0, vh_2, vh_4, vh_6: std_logic ;
 
begin
   g1000 : AND2I0 port map ( Q=>vh_0, A=>B_3, B=>A_3);
   g1001 : OR2I0 port map ( Q=>Z_3, A=>vh_0, B=>C_3);
   g1002 : AND2I0 port map ( Q=>vh_2, A=>B_2, B=>A_2);
   g1003 : OR2I0 port map ( Q=>Z_2, A=>vh_2, B=>C_2);
   g1004 : AND2I0 port map ( Q=>vh_4, A=>B_1, B=>A_1);
   g1005 : OR2I0 port map ( Q=>Z_1, A=>vh_4, B=>C_1);
   g1006 : AND2I0 port map ( Q=>vh_6, A=>B_0, B=>A_0);
   g1007 : OR2I0 port map ( Q=>Z_0, A=>vh_6, B=>C_0);

end exemplar ;