-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC1.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\LOGIC1.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP15.$$$ 
-- Version V2.1.4
-- Definition of  LOGIC1
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Fri Mar  3 18:06:44 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity LOGIC1 is
   port (
      A_3, A_2, A_1, A_0, B_3, B_2, B_1, B_0 : in std_logic ;
      Z_3, Z_2, Z_1, Z_0 : out std_logic) ;
end LOGIC1 ;

architecture exemplar of LOGIC1 is
   signal
      vh_0, vh_1, vh_2, vh_3, vh_4, vh_5, vh_6, vh_7, vh_8, vh_9, vh_10, 
      vh_11: std_logic ;
 
begin
   g1000 : AND2I1 port map ( Q=>vh_0, A=>B_3, B=>A_3);
   g1001 : AND2I1 port map ( Q=>vh_1, A=>B_2, B=>A_2);
   g1002 : AND2I1 port map ( Q=>vh_2, A=>B_1, B=>A_1);
   g1003 : AND3I2 port map ( Q=>vh_3, A=>A_0, B=>B_0, C=>vh_2);
   g1004 : AND2I1 port map ( Q=>vh_4, A=>A_1, B=>B_1);
   g1005 : AND2I2 port map ( Q=>vh_5, A=>vh_3, B=>vh_4);
   g1006 : AND2I2 port map ( Q=>vh_6, A=>vh_1, B=>vh_5);
   g1007 : AND2I1 port map ( Q=>vh_7, A=>A_2, B=>B_2);
   g1008 : AND2I2 port map ( Q=>vh_8, A=>vh_6, B=>vh_7);
   g1009 : AND2I2 port map ( Q=>vh_9, A=>vh_0, B=>vh_8);
   g1010 : AND2I1 port map ( Q=>vh_10, A=>A_3, B=>B_3);
   g1011 : OR2I0 port map ( Q=>vh_11, A=>vh_9, B=>vh_10);
   g1012 : MUX2X0 port map ( Q=>Z_3, A=>B_3, B=>A_3, S=>vh_11);
   g1013 : MUX2X0 port map ( Q=>Z_2, A=>B_2, B=>A_2, S=>vh_11);
   g1014 : MUX2X0 port map ( Q=>Z_1, A=>B_1, B=>A_1, S=>vh_11);
   g1015 : MUX2X0 port map ( Q=>Z_0, A=>B_0, B=>A_0, S=>vh_11);

end exemplar ;