-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC12.VHD D:\EXEMPLAR\TUT
-- ORIAL\HARDWARE\LOGIC12.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP4.$$$ 
-- Version V2.1.4
-- Definition of  LOGIC12
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Thu Mar 16 06:58:58 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity LOGIC12 is
   port (
      A_7, A_6, A_5, A_4, A_3, A_2, A_1, A_0, B_7, B_6, B_5, B_4, B_3, B_2, 
      B_1, B_0 : in std_logic ;
      S_7, S_6, S_5, S_4, S_3, S_2, S_1, S_0 : inout std_logic;
      FAILED : out std_logic) ;
end LOGIC12 ;

architecture exemplar of LOGIC12 is
   signal
      vh_0, vh_1, vh_2, vh_3, vh_4, vh_5, vh_6, vh_7, vh_9, vh_11, vh_13, 
      vh_15, vh_17, vh_19, vh_20, vh_23, vh_24, vh_25, vh_26, vh_27, vh_28, 
      vh_29, vh_30, vh_31, vh_32, vh_33, vh_34, vh_35, vh_36, vh_37, vh_38, 
      vh_39, vh_40, vh_41, vh_42, vh_43, vh_44, vh_45, vh_46, vh_47, vh_48, 
      vh_49, vh_50, vh_51, vh_52, vh_53, vh_54, vh_55, vh_56, vh_57, vh_58, 
      vh_59, vh_60, vh_61, vh_62, vh_63, vh_64, vh_65, vh_66, vh_67, vh_68, 
      vh_69, vh_70, vh_71, SI_29, vh_72, vh_73, vh_74, vh_75, vh_76, vh_77, 
      vh_78, vh_79, vh_80, vh_81, vh_82, vh_83, vh_84, vh_85, vh_86, vh_87, 
      vh_88, vh_89, vh_90, vh_91, vh_92, vh_93, vh_94, vh_95, vh_96, vh_97, 
      vh_98, vh_99, vh_100, US2_0, vh_101, vh_102, vh_103, vh_104, vh_105, 
      vh_106, vh_107, vh_108, vh_109, vh_110, vh_111, vh_112, vh_113, vh_114, 
      vh_115, vh_116, vh_117, vh_118, vh_119, vh_120, vh_121, vh_122, vh_123, 
      vh_124, vh_125, vh_126, vh_127, vh_128, vh_129, vh_130, vh_131, vh_132, 
      vh_133, vh_134, vh_135, vh_136, vh_137, vh_138, vh_139, vh_140, vh_141, 
      vh_142, vh_143, vh_144, vh_145, vh_146, vh_147, vh_148, vh_149, vh_150, 
      vh_151, vh_152, vh_153, vh_154, vh_155, vh_156, vh_157, vh_158, vh_159, 
      vh_160, vh_161, vh_162, URS2_0, vh_163, vh_164, vh_165, vh_166, vh_167, 
      vh_168, RS1_1, vh_169: std_logic ;
 
begin
   g1000 : AND2I0 port map ( Q=>vh_0, A=>B_0, B=>A_0);
   g1001 : MAJ3I0 port map ( Q=>vh_1, A=>B_1, B=>vh_0, C=>A_1);
   g1002 : MAJ3I0 port map ( Q=>vh_2, A=>B_2, B=>vh_1, C=>A_2);
   g1003 : MAJ3I0 port map ( Q=>vh_3, A=>B_3, B=>vh_2, C=>A_3);
   g1004 : MAJ3I0 port map ( Q=>vh_4, A=>B_4, B=>vh_3, C=>A_4);
   g1005 : MAJ3I0 port map ( Q=>vh_5, A=>B_5, B=>vh_4, C=>A_5);
   g1006 : MAJ3I0 port map ( Q=>vh_6, A=>B_6, B=>vh_5, C=>A_6);
   g1007 : XNOR3I0 port map ( Q=>vh_7, A=>B_7, B=>vh_6, C=>A_7);
   g1008 : INV port map ( Q=>S_7, A=>vh_7);
   g1009 : XNOR3I0 port map ( Q=>vh_9, A=>B_6, B=>vh_5, C=>A_6);
   g1010 : INV port map ( Q=>S_6, A=>vh_9);
   g1011 : XNOR3I0 port map ( Q=>vh_11, A=>B_5, B=>vh_4, C=>A_5);
   g1012 : INV port map ( Q=>S_5, A=>vh_11);
   g1013 : XNOR3I0 port map ( Q=>vh_13, A=>B_4, B=>vh_3, C=>A_4);
   g1014 : INV port map ( Q=>S_4, A=>vh_13);
   g1015 : XNOR3I0 port map ( Q=>vh_15, A=>B_3, B=>vh_2, C=>A_3);
   g1016 : INV port map ( Q=>S_3, A=>vh_15);
   g1017 : XNOR3I0 port map ( Q=>vh_17, A=>B_2, B=>vh_1, C=>A_2);
   g1018 : INV port map ( Q=>S_2, A=>vh_17);
   g1019 : OR2I2 port map ( Q=>vh_19, A=>B_0, B=>A_0);
   g1020 : XOR3I0 port map ( Q=>vh_20, A=>B_1, B=>vh_19, C=>A_1);
   g1021 : INV port map ( Q=>S_1, A=>vh_20);
   g1022 : MUX2X2 port map ( Q=>S_0, A=>B_0, B=>B_0, S=>A_0);
   g1023 : MUX2X1 port map ( Q=>vh_23, A=>B_0, B=>B_0, S=>A_0);
   g1024 : AND2I2 port map ( Q=>vh_24, A=>vh_17, B=>vh_23);
   g1025 : AND2I0 port map ( Q=>vh_25, A=>vh_15, B=>vh_20);
   g1026 : AND2I1 port map ( Q=>vh_26, A=>vh_24, B=>vh_25);
   g1027 : AND2I2 port map ( Q=>vh_27, A=>vh_15, B=>vh_20);
   g1028 : AND2I2 port map ( Q=>vh_28, A=>vh_26, B=>vh_27);
   g1029 : MUX2X1 port map ( Q=>vh_29, A=>vh_17, B=>vh_17, S=>S_0);
   g1030 : MUX2X1 port map ( Q=>vh_30, A=>vh_28, B=>vh_28, S=>vh_29);
   g1031 : AND2I2 port map ( Q=>vh_31, A=>vh_15, B=>vh_20);
   g1032 : OR2I0 port map ( Q=>vh_32, A=>vh_25, B=>vh_31);
   g1033 : MUX2X2 port map ( Q=>vh_33, A=>vh_24, B=>vh_24, S=>vh_32);
   g1034 : AND2I0 port map ( Q=>vh_34, A=>vh_30, B=>vh_33);
   g1035 : AND2I2 port map ( Q=>vh_35, A=>vh_9, B=>vh_13);
   g1036 : AND2I0 port map ( Q=>vh_36, A=>vh_7, B=>vh_11);
   g1037 : AND2I2 port map ( Q=>vh_37, A=>vh_7, B=>vh_11);
   g1038 : OR2I0 port map ( Q=>vh_38, A=>vh_36, B=>vh_37);
   g1039 : MUX2X2 port map ( Q=>vh_39, A=>vh_35, B=>vh_35, S=>vh_38);
   g1040 : AND2I1 port map ( Q=>vh_40, A=>vh_35, B=>vh_36);
   g1041 : AND2I2 port map ( Q=>vh_41, A=>vh_7, B=>vh_11);
   g1042 : AND2I2 port map ( Q=>vh_42, A=>vh_40, B=>vh_41);
   g1043 : XOR3I0 port map ( Q=>vh_43, A=>B_6, B=>vh_5, C=>A_6);
   g1044 : MUX2X2 port map ( Q=>vh_44, A=>vh_13, B=>vh_13, S=>vh_43);
   g1045 : AND2I1 port map ( Q=>vh_45, A=>vh_42, B=>vh_44);
   g1046 : AND2I1 port map ( Q=>vh_46, A=>vh_44, B=>vh_42);
   g1047 : AND2I2 port map ( Q=>vh_47, A=>vh_45, B=>vh_46);
   g1048 : AND2I1 port map ( Q=>vh_48, A=>vh_39, B=>vh_47);
   g1049 : AND2I0 port map ( Q=>vh_49, A=>vh_34, B=>vh_48);
   g1050 : MUX2X2 port map ( Q=>vh_50, A=>vh_17, B=>vh_17, S=>S_0);
   g1051 : AND3I1 port map ( Q=>vh_51, A=>vh_28, B=>vh_50, C=>vh_33);
   g1052 : AND3I2 port map ( Q=>vh_52, A=>vh_33, B=>vh_28, C=>vh_50);
   g1053 : AND2I2 port map ( Q=>vh_53, A=>vh_51, B=>vh_52);
   g1054 : AND3I1 port map ( Q=>vh_54, A=>vh_42, B=>vh_44, C=>vh_39);
   g1055 : AND3I2 port map ( Q=>vh_55, A=>vh_39, B=>vh_42, C=>vh_44);
   g1056 : AND2I2 port map ( Q=>vh_56, A=>vh_54, B=>vh_55);
   g1057 : AND2I0 port map ( Q=>vh_57, A=>vh_53, B=>vh_56);
   g1058 : AND2I2 port map ( Q=>vh_58, A=>vh_53, B=>vh_56);
   g1059 : OR2I0 port map ( Q=>vh_59, A=>vh_57, B=>vh_58);
   g1060 : MUX2X2 port map ( Q=>vh_60, A=>vh_49, B=>vh_49, S=>vh_59);
   g1061 : AND2I1 port map ( Q=>vh_61, A=>vh_49, B=>vh_57);
   g1062 : AND2I2 port map ( Q=>vh_62, A=>vh_53, B=>vh_56);
   g1063 : AND2I2 port map ( Q=>vh_63, A=>vh_61, B=>vh_62);
   g1064 : AND2I1 port map ( Q=>vh_64, A=>vh_34, B=>vh_48);
   g1065 : AND2I1 port map ( Q=>vh_65, A=>vh_48, B=>vh_34);
   g1066 : AND2I2 port map ( Q=>vh_66, A=>vh_64, B=>vh_65);
   g1067 : AND2I1 port map ( Q=>vh_67, A=>vh_63, B=>vh_66);
   g1068 : AND2I1 port map ( Q=>vh_68, A=>vh_66, B=>vh_63);
   g1069 : AND2I2 port map ( Q=>vh_69, A=>vh_67, B=>vh_68);
   g1070 : AND2I1 port map ( Q=>vh_70, A=>vh_60, B=>vh_69);
   g1071 : AND2I0 port map ( Q=>vh_71, A=>A_2, B=>A_0);
   g1072 : MAJ3I0 port map ( Q=>SI_29, A=>A_1, B=>vh_71, C=>A_3);
   g1073 : XOR3I0 port map ( Q=>vh_72, A=>A_2, B=>SI_29, C=>A_0);
   g1074 : OR2I2 port map ( Q=>vh_73, A=>A_2, B=>A_0);
   g1075 : XOR3I0 port map ( Q=>vh_74, A=>A_3, B=>vh_73, C=>A_1);
   g1076 : AND2I0 port map ( Q=>vh_75, A=>vh_72, B=>vh_74);
   g1077 : AND2I0 port map ( Q=>vh_76, A=>A_6, B=>A_4);
   g1078 : MAJ3I0 port map ( Q=>vh_77, A=>A_5, B=>vh_76, C=>A_7);
   g1079 : XOR3I0 port map ( Q=>vh_78, A=>A_6, B=>vh_77, C=>A_4);
   g1080 : OR2I2 port map ( Q=>vh_79, A=>A_6, B=>A_4);
   g1081 : XOR3I0 port map ( Q=>vh_80, A=>A_7, B=>vh_79, C=>A_5);
   g1082 : AND2I0 port map ( Q=>vh_81, A=>vh_78, B=>vh_80);
   g1083 : AND2I0 port map ( Q=>vh_82, A=>vh_75, B=>vh_81);
   g1084 : INV port map ( Q=>vh_83, A=>SI_29);
   g1085 : MUX2X1 port map ( Q=>vh_84, A=>A_2, B=>A_2, S=>A_0);
   g1086 : AND3I1 port map ( Q=>vh_85, A=>vh_83, B=>vh_84, C=>vh_74);
   g1087 : AND3I1 port map ( Q=>vh_86, A=>SI_29, B=>vh_74, C=>vh_84);
   g1088 : AND2I2 port map ( Q=>vh_87, A=>vh_85, B=>vh_86);
   g1089 : INV port map ( Q=>vh_88, A=>vh_77);
   g1090 : MUX2X1 port map ( Q=>vh_89, A=>A_6, B=>A_6, S=>A_4);
   g1091 : AND3I1 port map ( Q=>vh_90, A=>vh_88, B=>vh_89, C=>vh_80);
   g1092 : AND3I1 port map ( Q=>vh_91, A=>vh_77, B=>vh_80, C=>vh_89);
   g1093 : AND2I2 port map ( Q=>vh_92, A=>vh_90, B=>vh_91);
   g1094 : AND2I0 port map ( Q=>vh_93, A=>vh_87, B=>vh_92);
   g1095 : AND2I2 port map ( Q=>vh_94, A=>vh_87, B=>vh_92);
   g1096 : OR2I0 port map ( Q=>vh_95, A=>vh_93, B=>vh_94);
   g1097 : MUX2X2 port map ( Q=>vh_96, A=>vh_82, B=>vh_82, S=>vh_95);
   g1098 : AND2I1 port map ( Q=>vh_97, A=>vh_82, B=>vh_93);
   g1099 : AND2I2 port map ( Q=>vh_98, A=>vh_87, B=>vh_92);
   g1100 : AND2I2 port map ( Q=>vh_99, A=>vh_97, B=>vh_98);
   g1101 : XNOR3I0 port map ( Q=>vh_100, A=>A_6, B=>vh_77, C=>A_4);
   g1102 : OR2I1 port map ( Q=>US2_0, A=>vh_100, B=>vh_80);
   g1103 : MUX2X2 port map ( Q=>vh_101, A=>vh_75, B=>vh_75, S=>US2_0);
   g1104 : AND2I1 port map ( Q=>vh_102, A=>vh_99, B=>vh_101);
   g1105 : AND2I1 port map ( Q=>vh_103, A=>vh_101, B=>vh_99);
   g1106 : AND2I2 port map ( Q=>vh_104, A=>vh_102, B=>vh_103);
   g1107 : AND2I1 port map ( Q=>vh_105, A=>vh_96, B=>vh_104);
   g1108 : AND2I0 port map ( Q=>vh_106, A=>B_2, B=>B_0);
   g1109 : MAJ3I0 port map ( Q=>vh_107, A=>B_1, B=>vh_106, C=>B_3);
   g1110 : XOR3I0 port map ( Q=>vh_108, A=>B_2, B=>vh_107, C=>B_0);
   g1111 : OR2I2 port map ( Q=>vh_109, A=>B_2, B=>B_0);
   g1112 : XOR3I0 port map ( Q=>vh_110, A=>B_3, B=>vh_109, C=>B_1);
   g1113 : AND2I0 port map ( Q=>vh_111, A=>vh_108, B=>vh_110);
   g1114 : AND2I0 port map ( Q=>vh_112, A=>B_6, B=>B_4);
   g1115 : MAJ3I0 port map ( Q=>vh_113, A=>B_5, B=>vh_112, C=>B_7);
   g1116 : XOR3I0 port map ( Q=>vh_114, A=>B_6, B=>vh_113, C=>B_4);
   g1117 : OR2I2 port map ( Q=>vh_115, A=>B_6, B=>B_4);
   g1118 : XOR3I0 port map ( Q=>vh_116, A=>B_7, B=>vh_115, C=>B_5);
   g1119 : AND2I0 port map ( Q=>vh_117, A=>vh_114, B=>vh_116);
   g1120 : AND2I0 port map ( Q=>vh_118, A=>vh_111, B=>vh_117);
   g1121 : INV port map ( Q=>vh_119, A=>vh_107);
   g1122 : MUX2X1 port map ( Q=>vh_120, A=>B_2, B=>B_2, S=>B_0);
   g1123 : AND3I1 port map ( Q=>vh_121, A=>vh_119, B=>vh_120, C=>vh_110);
   g1124 : AND3I1 port map ( Q=>vh_122, A=>vh_107, B=>vh_110, C=>vh_120);
   g1125 : AND2I2 port map ( Q=>vh_123, A=>vh_121, B=>vh_122);
   g1126 : INV port map ( Q=>vh_124, A=>vh_113);
   g1127 : MUX2X1 port map ( Q=>vh_125, A=>B_6, B=>B_6, S=>B_4);
   g1128 : AND3I1 port map ( Q=>vh_126, A=>vh_124, B=>vh_125, C=>vh_116);
   g1129 : AND3I1 port map ( Q=>vh_127, A=>vh_113, B=>vh_116, C=>vh_125);
   g1130 : AND2I2 port map ( Q=>vh_128, A=>vh_126, B=>vh_127);
   g1131 : AND2I0 port map ( Q=>vh_129, A=>vh_123, B=>vh_128);
   g1132 : AND2I2 port map ( Q=>vh_130, A=>vh_123, B=>vh_128);
   g1133 : OR2I0 port map ( Q=>vh_131, A=>vh_129, B=>vh_130);
   g1134 : MUX2X2 port map ( Q=>vh_132, A=>vh_118, B=>vh_118, S=>vh_131);
   g1135 : AND2I1 port map ( Q=>vh_133, A=>vh_118, B=>vh_129);
   g1136 : AND2I2 port map ( Q=>vh_134, A=>vh_123, B=>vh_128);
   g1137 : AND2I2 port map ( Q=>vh_135, A=>vh_133, B=>vh_134);
   g1138 : XNOR3I0 port map ( Q=>vh_136, A=>B_6, B=>vh_113, C=>B_4);
   g1139 : OR2I1 port map ( Q=>vh_137, A=>vh_136, B=>vh_116);
   g1140 : MUX2X2 port map ( Q=>vh_138, A=>vh_111, B=>vh_111, S=>vh_137);
   g1141 : AND2I1 port map ( Q=>vh_139, A=>vh_135, B=>vh_138);
   g1142 : AND2I1 port map ( Q=>vh_140, A=>vh_138, B=>vh_135);
   g1143 : AND2I2 port map ( Q=>vh_141, A=>vh_139, B=>vh_140);
   g1144 : AND2I1 port map ( Q=>vh_142, A=>vh_132, B=>vh_141);
   g1145 : AND2I0 port map ( Q=>vh_143, A=>vh_105, B=>vh_142);
   g1146 : AND3I1 port map ( Q=>vh_144, A=>vh_99, B=>vh_101, C=>vh_96);
   g1147 : AND3I2 port map ( Q=>vh_145, A=>vh_96, B=>vh_99, C=>vh_101);
   g1148 : AND2I2 port map ( Q=>vh_146, A=>vh_144, B=>vh_145);
   g1149 : AND3I1 port map ( Q=>vh_147, A=>vh_135, B=>vh_138, C=>vh_132);
   g1150 : AND3I2 port map ( Q=>vh_148, A=>vh_132, B=>vh_135, C=>vh_138);
   g1151 : AND2I2 port map ( Q=>vh_149, A=>vh_147, B=>vh_148);
   g1152 : AND2I0 port map ( Q=>vh_150, A=>vh_146, B=>vh_149);
   g1153 : AND2I1 port map ( Q=>vh_151, A=>vh_143, B=>vh_150);
   g1154 : AND2I2 port map ( Q=>vh_152, A=>vh_146, B=>vh_149);
   g1155 : AND2I2 port map ( Q=>vh_153, A=>vh_151, B=>vh_152);
   g1156 : AND2I1 port map ( Q=>vh_154, A=>vh_105, B=>vh_142);
   g1157 : AND2I1 port map ( Q=>vh_155, A=>vh_142, B=>vh_105);
   g1158 : AND2I2 port map ( Q=>vh_156, A=>vh_154, B=>vh_155);
   g1159 : AND2I1 port map ( Q=>vh_157, A=>vh_153, B=>vh_156);
   g1160 : AND2I1 port map ( Q=>vh_158, A=>vh_156, B=>vh_153);
   g1161 : AND2I2 port map ( Q=>vh_159, A=>vh_157, B=>vh_158);
   g1162 : AND2I2 port map ( Q=>vh_160, A=>vh_146, B=>vh_149);
   g1163 : OR2I0 port map ( Q=>vh_161, A=>vh_150, B=>vh_160);
   g1164 : MUX2X2 port map ( Q=>vh_162, A=>vh_143, B=>vh_143, S=>vh_161);
   g1165 : OR2I1 port map ( Q=>URS2_0, A=>vh_159, B=>vh_162);
   g1166 : MUX2X1 port map ( Q=>vh_163, A=>vh_70, B=>vh_70, S=>URS2_0);
   g1167 : AND3I1 port map ( Q=>vh_164, A=>vh_153, B=>vh_156, C=>vh_162);
   g1168 : AND3I2 port map ( Q=>vh_165, A=>vh_162, B=>vh_153, C=>vh_156);
   g1169 : AND2I2 port map ( Q=>vh_166, A=>vh_164, B=>vh_165);
   g1170 : AND3I1 port map ( Q=>vh_167, A=>vh_63, B=>vh_66, C=>vh_60);
   g1171 : AND3I2 port map ( Q=>vh_168, A=>vh_60, B=>vh_63, C=>vh_66);
   g1172 : OR2I0 port map ( Q=>RS1_1, A=>vh_167, B=>vh_168);
   g1173 : MUX2X1 port map ( Q=>vh_169, A=>vh_166, B=>vh_166, S=>RS1_1);
   g1174 : OR2I0 port map ( Q=>FAILED, A=>vh_163, B=>vh_169);

end exemplar ;