-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC14.VHD D:\EXEMPLAR\TUT
-- ORIAL\HARDWARE\LOGIC14.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP16.$$$ 
-- Version V2.1.4
-- Definition of  LOGIC14
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Thu Mar 16 14:07:55 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity LOGIC14 is
   port (
      A, B : in std_logic ;
      X, Z : out std_logic) ;
end LOGIC14 ;

architecture exemplar of LOGIC14 is
 
begin
   X <= B ;
   g1000 : MUX2X1 port map ( Q=>Z, A=>B, B=>B, S=>A);

end exemplar ;