-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC2.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\LOGIC2.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP17.$$$ 
-- Version V2.1.4
-- Definition of  LOGIC2
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Fri Mar  3 19:44:05 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity LOGIC2 is
   port (
      A_3, A_2, A_1, A_0, B_3, B_2, B_1, B_0, COMP_IN_2, COMP_IN_1, 
      COMP_IN_0 : in std_logic ;
      COMP_OUT_2, COMP_OUT_1, COMP_OUT_0 : out std_logic) ;
end LOGIC2 ;

architecture exemplar of LOGIC2 is
   signal
      vh_0, vh_1, vh_2, vh_3, vh_4, vh_5, vh_6, vh_7, vh_8, vh_9, vh_10, 
      vh_11, vh_12, vh_13, vh_14, vh_15, vh_16, vh_17, vh_18, vh_19, vh_22, 
      vh_23: std_logic ;
 
begin
   g1000 : AND2I1 port map ( Q=>vh_0, A=>A_3, B=>B_3);
   g1001 : AND2I1 port map ( Q=>vh_1, A=>B_3, B=>A_3);
   g1002 : AND2I1 port map ( Q=>vh_2, A=>A_2, B=>B_2);
   g1003 : AND2I1 port map ( Q=>vh_3, A=>B_2, B=>A_2);
   g1004 : AND2I1 port map ( Q=>vh_4, A=>A_1, B=>B_1);
   g1005 : AND2I1 port map ( Q=>vh_5, A=>B_1, B=>A_1);
   g1006 : AND3I2 port map ( Q=>vh_6, A=>A_0, B=>vh_5, C=>B_0);
   g1007 : AND2I2 port map ( Q=>vh_7, A=>vh_4, B=>vh_6);
   g1008 : AND2I2 port map ( Q=>vh_8, A=>vh_3, B=>vh_7);
   g1009 : AND2I2 port map ( Q=>vh_9, A=>vh_2, B=>vh_8);
   g1010 : AND2I2 port map ( Q=>vh_10, A=>vh_1, B=>vh_9);
   g1011 : AND2I2 port map ( Q=>vh_11, A=>vh_0, B=>vh_10);
   g1012 : AND3I2 port map ( Q=>vh_12, A=>B_0, B=>vh_4, C=>A_0);
   g1013 : AND2I2 port map ( Q=>vh_13, A=>vh_5, B=>vh_12);
   g1014 : AND2I2 port map ( Q=>vh_14, A=>vh_2, B=>vh_13);
   g1015 : AND2I2 port map ( Q=>vh_15, A=>vh_3, B=>vh_14);
   g1016 : AND2I2 port map ( Q=>vh_16, A=>vh_0, B=>vh_15);
   g1017 : AND2I2 port map ( Q=>vh_17, A=>vh_1, B=>vh_16);
   g1018 : AND2I0 port map ( Q=>vh_18, A=>vh_11, B=>vh_17);
   g1019 : AND2I0 port map ( Q=>vh_19, A=>COMP_IN_2, B=>vh_18);
   g1020 : OR2I1 port map ( Q=>COMP_OUT_2, A=>vh_19, B=>vh_11);
   g1021 : AND2I0 port map ( Q=>COMP_OUT_1, A=>COMP_IN_1, B=>vh_18);
   g1022 : AND2I0 port map ( Q=>vh_22, A=>COMP_IN_0, B=>vh_18);
   g1023 : AND2I1 port map ( Q=>vh_23, A=>vh_11, B=>vh_17);
   g1024 : OR2I0 port map ( Q=>COMP_OUT_0, A=>vh_22, B=>vh_23);

end exemplar ;