-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC9.VHD D:\EXEMPLAR\TUTO
-- RIAL\HARDWARE\LOGIC9.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP11.$$$ 
-- Version V2.1.4
-- Definition of  LOGIC9
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Fri Mar 10 19:49:29 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity LOGIC9 is
   port (
      A_7, A_6, A_5, A_4, A_3, A_2, A_1, A_0, B_7, B_6, B_5, B_4, B_3, B_2, 
      B_1, B_0, C_7, C_6, C_5, C_4, C_3, C_2, C_1, C_0, D_7, D_6, D_5, D_4, 
      D_3, D_2, D_1, D_0, S : in std_logic ;
      Z_7, Z_6, Z_5, Z_4, Z_3, Z_2, Z_1, Z_0 : out std_logic) ;
end LOGIC9 ;

architecture exemplar of LOGIC9 is
   signal
      BD_7, BD_6, vh_0, vh_1, vh_2, vh_3, vh_4, vh_5, vh_6, vh_7, vh_8, vh_9, 
      vh_10, vh_11, vh_12, vh_13, vh_14, vh_15, vh_16, vh_17, vh_18, vh_19, 
      vh_20, vh_21, vh_22, vh_23, vh_24, vh_25, vh_26, vh_27, vh_28, vh_29, 
      vh_30, vh_31, vh_32, vh_33, AC_6, vh_34, AC_7, vh_36, vh_37, AC_5, 
      vh_39, AC_4, vh_41, AC_3, vh_43, AC_2, vh_45, AC_1, vh_47, BD_0, vh_50, 
      vh_51: std_logic ;
 
begin
   g1000 : MUX2X0 port map ( Q=>BD_7, A=>D_7, B=>B_7, S=>vh_50);
   g1001 : MUX2X0 port map ( Q=>BD_6, A=>D_6, B=>B_6, S=>vh_50);
   g1002 : MUX2X3 port map ( Q=>vh_0, A=>D_0, B=>B_0, S=>vh_50);
   g1003 : MUX2X3 port map ( Q=>vh_1, A=>C_0, B=>A_0, S=>vh_50);
   g1004 : AND2I2 port map ( Q=>vh_2, A=>vh_0, B=>vh_1);
   g1005 : MUX2X3 port map ( Q=>vh_3, A=>D_1, B=>B_1, S=>vh_50);
   g1006 : MUX2X3 port map ( Q=>vh_4, A=>C_1, B=>A_1, S=>vh_50);
   g1007 : AND2I0 port map ( Q=>vh_5, A=>vh_3, B=>vh_4);
   g1008 : AND2I1 port map ( Q=>vh_6, A=>vh_2, B=>vh_5);
   g1009 : AND2I2 port map ( Q=>vh_7, A=>vh_3, B=>vh_4);
   g1010 : AND2I2 port map ( Q=>vh_8, A=>vh_6, B=>vh_7);
   g1011 : MUX2X3 port map ( Q=>vh_9, A=>D_2, B=>B_2, S=>vh_50);
   g1012 : MUX2X3 port map ( Q=>vh_10, A=>C_2, B=>A_2, S=>vh_50);
   g1013 : AND2I0 port map ( Q=>vh_11, A=>vh_9, B=>vh_10);
   g1014 : AND2I2 port map ( Q=>vh_12, A=>vh_8, B=>vh_11);
   g1015 : AND2I2 port map ( Q=>vh_13, A=>vh_9, B=>vh_10);
   g1016 : AND2I2 port map ( Q=>vh_14, A=>vh_12, B=>vh_13);
   g1017 : MUX2X3 port map ( Q=>vh_15, A=>D_3, B=>B_3, S=>vh_50);
   g1018 : MUX2X3 port map ( Q=>vh_16, A=>C_3, B=>A_3, S=>vh_50);
   g1019 : AND2I0 port map ( Q=>vh_17, A=>vh_15, B=>vh_16);
   g1020 : AND2I2 port map ( Q=>vh_18, A=>vh_14, B=>vh_17);
   g1021 : AND2I2 port map ( Q=>vh_19, A=>vh_15, B=>vh_16);
   g1022 : AND2I2 port map ( Q=>vh_20, A=>vh_18, B=>vh_19);
   g1023 : MUX2X3 port map ( Q=>vh_21, A=>D_4, B=>B_4, S=>vh_50);
   g1024 : MUX2X3 port map ( Q=>vh_22, A=>C_4, B=>A_4, S=>vh_51);
   g1025 : AND2I0 port map ( Q=>vh_23, A=>vh_21, B=>vh_22);
   g1026 : AND2I2 port map ( Q=>vh_24, A=>vh_20, B=>vh_23);
   g1027 : AND2I2 port map ( Q=>vh_25, A=>vh_21, B=>vh_22);
   g1028 : AND2I2 port map ( Q=>vh_26, A=>vh_24, B=>vh_25);
   g1029 : MUX2X3 port map ( Q=>vh_27, A=>D_5, B=>B_5, S=>vh_51);
   g1030 : MUX2X3 port map ( Q=>vh_28, A=>C_5, B=>A_5, S=>vh_51);
   g1031 : AND2I0 port map ( Q=>vh_29, A=>vh_27, B=>vh_28);
   g1032 : AND2I2 port map ( Q=>vh_30, A=>vh_26, B=>vh_29);
   g1033 : AND2I2 port map ( Q=>vh_31, A=>vh_27, B=>vh_28);
   g1034 : AND2I2 port map ( Q=>vh_32, A=>vh_30, B=>vh_31);
   g1035 : INV port map ( Q=>vh_33, A=>vh_32);
   g1036 : MUX2X0 port map ( Q=>AC_6, A=>C_6, B=>A_6, S=>vh_51);
   g1037 : MAJ3I0 port map ( Q=>vh_34, A=>BD_6, B=>vh_33, C=>AC_6);
   g1038 : MUX2X0 port map ( Q=>AC_7, A=>C_7, B=>A_7, S=>vh_51);
   g1039 : XOR3I0 port map ( Q=>Z_7, A=>BD_7, B=>vh_34, C=>AC_7);
   g1040 : MUX2X3 port map ( Q=>vh_36, A=>D_6, B=>B_6, S=>vh_51);
   g1041 : MUX2X2 port map ( Q=>vh_37, A=>vh_36, B=>vh_36, S=>AC_6);
   g1042 : MUX2X2 port map ( Q=>Z_6, A=>vh_32, B=>vh_32, S=>vh_37);
   g1043 : MUX2X0 port map ( Q=>AC_5, A=>C_5, B=>A_5, S=>vh_51);
   g1044 : MUX2X2 port map ( Q=>vh_39, A=>vh_27, B=>vh_27, S=>AC_5);
   g1045 : MUX2X2 port map ( Q=>Z_5, A=>vh_26, B=>vh_26, S=>vh_39);
   g1046 : MUX2X0 port map ( Q=>AC_4, A=>C_4, B=>A_4, S=>vh_51);
   g1047 : MUX2X2 port map ( Q=>vh_41, A=>vh_21, B=>vh_21, S=>AC_4);
   g1048 : MUX2X2 port map ( Q=>Z_4, A=>vh_20, B=>vh_20, S=>vh_41);
   g1049 : MUX2X0 port map ( Q=>AC_3, A=>C_3, B=>A_3, S=>vh_51);
   g1050 : MUX2X2 port map ( Q=>vh_43, A=>vh_15, B=>vh_15, S=>AC_3);
   g1051 : MUX2X2 port map ( Q=>Z_3, A=>vh_14, B=>vh_14, S=>vh_43);
   g1052 : MUX2X0 port map ( Q=>AC_2, A=>C_2, B=>A_2, S=>vh_51);
   g1053 : MUX2X2 port map ( Q=>vh_45, A=>vh_9, B=>vh_9, S=>AC_2);
   g1054 : MUX2X2 port map ( Q=>Z_2, A=>vh_8, B=>vh_8, S=>vh_45);
   g1055 : MUX2X0 port map ( Q=>AC_1, A=>C_1, B=>A_1, S=>vh_51);
   g1056 : MUX2X2 port map ( Q=>vh_47, A=>vh_3, B=>vh_3, S=>AC_1);
   g1057 : MUX2X1 port map ( Q=>Z_1, A=>vh_2, B=>vh_2, S=>vh_47);
   g1058 : MUX2X0 port map ( Q=>BD_0, A=>D_0, B=>B_0, S=>vh_51);
   g1059 : MUX2X1 port map ( Q=>Z_0, A=>vh_1, B=>vh_1, S=>BD_0);
   g1060 : BUFF port map ( Q=>vh_50, A=>S);
   g1061 : BUFF port map ( Q=>vh_51, A=>S);

end exemplar ;