-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\MACHINE2.VHD D:\EXEMPLAR\TU
-- TORIAL\HARDWARE\MACHINE2.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP31.$$$ 
-- Version V2.1.4
-- Definition of  MACHINE2
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Thu Mar 16 16:10:59 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity MACHINE2 is
   port (
      X, R, CLK : in std_logic ;
      Z : out std_logic) ;
end MACHINE2 ;

architecture exemplar of MACHINE2 is
   signal
      PRESENT_STATE_0, PRESENT_STATE_1, vh_2, vh_5, vh_6, vh_7: std_logic ;
 
begin
   g1000 : AND2I0 port map ( Q=>Z, A=>PRESENT_STATE_0, B=>PRESENT_STATE_1);
   g1001 : AND2I1 port map ( Q=>vh_2, A=>X, B=>R);
   g1002 : AND4I2 port map ( Q=>vh_5, A=>X, B=>PRESENT_STATE_1, C=>PRESENT_STATE_0, D=>R);
   g1003 : AND3I2 port map ( Q=>vh_6, A=>PRESENT_STATE_0, B=>R, C=>X);
   g1004 : OR2I0 port map ( Q=>vh_7, A=>vh_5, B=>vh_6);
   vh_9 : DFF port map ( CLK=>CLK, D=>vh_2, Q=>PRESENT_STATE_0);
   vh_10 : DFF port map ( CLK=>CLK, D=>vh_7, Q=>PRESENT_STATE_1);

end exemplar ;