-- 
-- Program 
-- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\REG4.VHD D:\EXEMPLAR\TUTORI
-- AL\HARDWARE\REG4.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP21.$$$ 
-- Version V2.1.4
-- Definition of  REG4
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Thu Mar 16 14:51:09 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

LIBRARY exemplar;
USE exemplar.Cypress_pASIC.ALL;

entity REG4 is
   port (
      D, C, A : in std_logic ;
      Z : out std_logic) ;
end REG4 ;

architecture exemplar of REG4 is
   signal
      FLAGr1: std_logic ;
 
begin
   g1000 : AND3I0 port map ( Q=>Z, A=>FLAGr1, B=>A, C=>D);
   vh_3 : DFF port map ( CLK=>C, D=>D, Q=>FLAGr1);

end exemplar ;