-- 
-- Program 
-- C:\EXEMPLAR\BIN\PC\FPGA.EXE C:\VHDL\NAVABI\SER_ADD.VHD C:\VHDL\NAVABI\HARDWA
-- RE\SER_ADD.VHD -COMMAND_FILE=C:\EXEMPLAR\DEMO\TMP2.$$$ 
-- Version V2.1.10
-- Definition of  SER_ADD
-- 
-- VHDL Structural Description, created by
-- Exemplar Logic's CORE
--      Tue Apr 11 07:39:54 1995
-- 
-- 
-- 

library ieee ;
use ieee.std_logic_1164.all ;

entity SER_ADD is
   port (
      A, B, START, CLOCK : in std_logic ;
      DONE, Z_7, Z_6, Z_5, Z_4, Z_3, Z_2, Z_1, Z_0 : inout std_logic) ;
end SER_ADD ;

architecture exemplar of SER_ADD is
   component AND3I0
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND2I2
      port (
         A, B : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND3I1
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND2I1
      port (
         A, B : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND4I1
      port (
         A, B, C, D : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component OR2I0
      port (
         A, B : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component MUX2X0
      port (
         A, B, S : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND3I2
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component AND3I3
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component XOR3I0
      port (
         A, B, C : in std_logic ;
         Q : out std_logic) ;
   end component ;
   component DFF
      port (
         CLK, D : in std_logic ;
         Q : out std_logic) ;
   end component ;
   signal
      COUNT_0, COUNT_1, COUNT_2, BUSY, CARRY, vh_10, vh_11, vh_12, vh_13, 
      vh_14, vh_15, vh_16, vh_17, vh_18, vh_19, vh_20, vh_21, vh_24, vh_25, 
      vh_26, vh_29, vh_30, vh_31, vh_34, vh_37, vh_38, vh_39, vh_40, vh_43, 
      vh_44, vh_45, vh_48, vh_51, vh_54, vh_57, vh_60, vh_63, vh_66, vh_69, 
      vh_70: std_logic ;
 
begin
   g1000 : AND3I0 port map ( Q=>vh_10, A=>COUNT_2, B=>COUNT_0, C=>COUNT_1);
   g1001 : AND2I2 port map ( Q=>vh_11, A=>START, B=>BUSY);
   g1002 : AND2I2 port map ( Q=>vh_12, A=>vh_10, B=>vh_11);
   g1003 : AND3I1 port map ( Q=>vh_13, A=>COUNT_2, B=>COUNT_1, C=>COUNT_0);
   g1004 : AND2I1 port map ( Q=>vh_14, A=>COUNT_0, B=>COUNT_1);
   g1005 : AND2I2 port map ( Q=>vh_15, A=>vh_13, B=>vh_14);
   g1006 : AND2I1 port map ( Q=>vh_16, A=>vh_12, B=>vh_15);
   g1007 : AND4I1 port map ( Q=>vh_17, A=>COUNT_1, B=>COUNT_2, C=>COUNT_0, 
      D=>vh_11);
   g1008 : OR2I0 port map ( Q=>vh_18, A=>vh_10, B=>vh_11);
   g1009 : MUX2X0 port map ( Q=>vh_19, A=>COUNT_2, B=>vh_17, S=>vh_18);
   g1010 : AND2I1 port map ( Q=>vh_20, A=>COUNT_0, B=>vh_19);
   g1011 : OR2I0 port map ( Q=>vh_21, A=>vh_16, B=>vh_20);
   g1012 : AND3I1 port map ( Q=>vh_24, A=>vh_12, B=>COUNT_2, C=>COUNT_1);
   g1013 : AND2I1 port map ( Q=>vh_25, A=>COUNT_1, B=>vh_19);
   g1014 : OR2I0 port map ( Q=>vh_26, A=>vh_24, B=>vh_25);
   g1015 : AND3I2 port map ( Q=>vh_29, A=>COUNT_2, B=>vh_17, C=>vh_12);
   g1016 : AND2I1 port map ( Q=>vh_30, A=>vh_12, B=>COUNT_2);
   g1017 : OR2I0 port map ( Q=>vh_31, A=>vh_29, B=>vh_30);
   g1018 : AND2I2 port map ( Q=>vh_34, A=>vh_17, B=>vh_11);
   g1019 : AND3I1 port map ( Q=>vh_37, A=>A, B=>B, C=>vh_11);
   g1020 : AND3I3 port map ( Q=>vh_38, A=>vh_11, B=>B, C=>A);
   g1021 : AND2I1 port map ( Q=>vh_39, A=>CARRY, B=>vh_38);
   g1022 : OR2I0 port map ( Q=>vh_40, A=>vh_37, B=>vh_39);
   g1023 : XOR3I0 port map ( Q=>vh_43, A=>B, B=>CARRY, C=>A);
   g1024 : OR2I0 port map ( Q=>vh_44, A=>START, B=>BUSY);
   g1025 : MUX2X0 port map ( Q=>vh_45, A=>Z_7, B=>vh_43, S=>vh_44);
   g1026 : MUX2X0 port map ( Q=>vh_48, A=>Z_6, B=>Z_7, S=>vh_44);
   g1027 : MUX2X0 port map ( Q=>vh_51, A=>Z_5, B=>Z_6, S=>vh_44);
   g1028 : MUX2X0 port map ( Q=>vh_54, A=>Z_4, B=>Z_5, S=>vh_44);
   g1029 : MUX2X0 port map ( Q=>vh_57, A=>Z_3, B=>Z_4, S=>vh_44);
   g1030 : MUX2X0 port map ( Q=>vh_60, A=>Z_2, B=>Z_3, S=>vh_44);
   g1031 : MUX2X0 port map ( Q=>vh_63, A=>Z_1, B=>Z_2, S=>vh_44);
   g1032 : MUX2X0 port map ( Q=>vh_66, A=>Z_0, B=>Z_1, S=>vh_44);
   g1033 : AND2I1 port map ( Q=>vh_69, A=>DONE, B=>START);
   g1034 : OR2I0 port map ( Q=>vh_70, A=>vh_17, B=>vh_69);
   vh_72 : DFF port map ( CLK=>CLOCK, D=>vh_21, Q=>COUNT_0);
   vh_73 : DFF port map ( CLK=>CLOCK, D=>vh_26, Q=>COUNT_1);
   vh_74 : DFF port map ( CLK=>CLOCK, D=>vh_31, Q=>COUNT_2);
   vh_75 : DFF port map ( CLK=>CLOCK, D=>vh_34, Q=>BUSY);
   vh_76 : DFF port map ( CLK=>CLOCK, D=>vh_40, Q=>CARRY);
   vh_77 : DFF port map ( CLK=>CLOCK, D=>vh_45, Q=>Z_7);
   vh_78 : DFF port map ( CLK=>CLOCK, D=>vh_48, Q=>Z_6);
   vh_79 : DFF port map ( CLK=>CLOCK, D=>vh_51, Q=>Z_5);
   vh_80 : DFF port map ( CLK=>CLOCK, D=>vh_54, Q=>Z_4);
   vh_81 : DFF port map ( CLK=>CLOCK, D=>vh_57, Q=>Z_3);
   vh_82 : DFF port map ( CLK=>CLOCK, D=>vh_60, Q=>Z_2);
   vh_83 : DFF port map ( CLK=>CLOCK, D=>vh_63, Q=>Z_1);
   vh_84 : DFF port map ( CLK=>CLOCK, D=>vh_66, Q=>Z_0);
   vh_85 : DFF port map ( CLK=>CLOCK, D=>vh_70, Q=>DONE);

end exemplar ;