-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY loadable_random_counter IS
  PORT (clock, preset, clear, preload : IN std_logic;
        count_in : IN std_logic_vector (3 DOWNTO 0);
        count_out : INOUT std_logic_vector (3 DOWNTO 0));
END loadable_random_counter;

ARCHITECTURE behavioral OF loadable_random_counter IS
BEGIN
  counting : PROCESS (clock, preset, clear, preload, count_in)
  BEGIN
    IF preset = '1' THEN
      count_out <= "1111";
    ELSIF clear = '1' THEN
      count_out <= "0000";
    ELSIF preload = '1' THEN
      count_out <= count_in;
    ELSIF (clock = '1' AND clock'EVENT) THEN
      CASE count_out IS
        WHEN "0000" => count_out <= "0110";
        WHEN "0001" => count_out <= "1010";
        WHEN "0010" => count_out <= "1011";
        WHEN "0011" => count_out <= "1110";
        WHEN "0100" => count_out <= "0010";
        WHEN "0101" => count_out <= "0101";
        WHEN "0110" => count_out <= "1101";
        WHEN "0111" => count_out <= "0000";
        WHEN "1000" => count_out <= "1100";
        WHEN "1001" => count_out <= "1111";
        WHEN "1010" => count_out <= "0001";
        WHEN "1011" => count_out <= "0100";
        WHEN "1100" => count_out <= "1001";
        WHEN "1101" => count_out <= "0011";
        WHEN "1110" => count_out <= "0111";
        WHEN "1111" => count_out <= "1000";
        WHEN OTHERS => NULL;
      END CASE;
    END IF;
  END PROCESS;
END behavioral;