-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY divider_counter IS
  PORT (clock, reset : IN std_logic; divide_out : OUT std_logic);
END;

ARCHITECTURE we_take_control OF divider_counter IS
  SIGNAL count : std_logic_vector (3 DOWNTO 0);
BEGIN
  dividing : PROCESS (clock)
  BEGIN
    IF (clock'EVENT and CLOCK = '1') THEN
      IF reset = '1' THEN 
        count <= "0000";
      ELSE 
        count <= count - "01";
      END IF;
      IF count = "0000" THEN
        divide_out <= '1';
        count <= "1100";
      ELSE
        divide_out <= '0';
      END IF;
    END IF;
  END PROCESS;
END we_take_control;