-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY and_or IS
  PORT (a, b, c : IN std_logic_vector (3 DOWNTO 0); 
        z : OUT std_logic_vector (3 DOWNTO 0));
END;

ARCHITECTURE dataflow OF and_or IS
BEGIN
  z <= (a AND b) OR c;
END dataflow;