-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;


ENTITY incomplete_if IS
  PORT (a, b : IN std_logic; 
        x, z : OUT std_logic);
END;

ARCHITECTURE behavioral OF incomplete_if IS
BEGIN
  PROCESS (a, b)
  BEGIN 
    z <= '0';
    IF a = b THEN z <= '1'; END IF;
    x <= b;
  END PROCESS;
END behavioral;