-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY seven_segment_decoder IS
  PORT (bcd_in : IN std_logic_vector (3 DOWNTO 0); 
        ssd_out : OUT std_logic_vector (6 DOWNTO 0));
END;

ARCHITECTURE dataflow OF seven_segment_decoder IS
BEGIN
  WITH bcd_in SELECT
   ssd_out <= "1111110" WHEN "0000",
              "0110000" WHEN "0001",      
              "1111001" WHEN "0010",      
              "0110000" WHEN "0011",      
              "1111001" WHEN "0100",      
              "1011011" WHEN "0101",      
              "1011111" WHEN "0110",      
              "1110000" WHEN "0111",      
              "1111111" WHEN "1000",      
              "1111011" WHEN "1001",      
              "1001111" WHEN OTHERS;
END dataflow;