-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core           --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;

ENTITY simple_alu IS
  PORT (a, b : IN std_logic_vector (3 DOWNTO 0); 
        code_in : IN std_logic_vector (2 DOWNTO 0); 
        flags : INOUT std_logic_vector (2 DOWNTO 0);
        z_out : OUT std_logic_vector (3 DOWNTO 0));
END;

ARCHITECTURE behavioral OF simple_alu IS
BEGIN
  alu : PROCESS (a, b, code_in)
    VARIABLE temp : std_logic_vector(4 DOWNTO 0);
  BEGIN
    flags <= "000";
    z_out <= "0000"; 
    IF code_in = "000" THEN
      z_out <= a;
    ELSIF code_in = "001" THEN
        z_out <= b;
    ELSIF code_in = "010" THEN
      z_out <= a AND b;
    ELSIF code_in = "011" THEN
      z_out <= a OR b;
    ELSIF code_in = "100" THEN
      temp := add2(a,b);
      z_out <= temp(3 DOWNTO 0);
      flags(2) <= temp(4);
    ELSIF code_in = "101" THEN
      temp := sub2(a,b);
      z_out <= temp(3 DOWNTO 0);
      flags(2) <= temp(4);
    ELSIF code_in(2 DOWNTO 1) = "11" THEN
      IF a > b THEN
        IF code_in(0) = '0' THEN
          z_out <= a;
          flags(1) <= '1';
        ELSE 
          z_out <= b;
        END IF;
      ELSIF b > a THEN
        IF code_in(0) = '0' THEN
          z_out <= b;
        ELSE
          z_out <= a;
          flags(0) <= '1';
        END IF;
      END IF;
    END IF;
  END PROCESS;
END behavioral;