-- -----------------------------------------------------------------------------
--  GLUE LOGIC BETWEEN IrDA/RS232/TEXT_BUFFER EPLD and COMPRESSION/RSA FLEXs  --
-- -----------------------------------------------------------------------------
--
--  File        : 'glue.vhd'
--  Author      : Lars Larsson 
-- 
--  Date        : February 10, 1999
--
--  Description : The design is a pice of glue logic between the EPM7160SLC84 
--                (IrDA-CoDec, RS232-UART, TEXT_BUFFER with RAM controller EPLD)
--                and two EPF10K10LC84 (data compressor/decompressor plus RSA 
--                processor FPGA) mounted on our FPGA-Praktikum PCB board.
--
--  Hint        : File 'components.vhd' (package components) is required.
-- 
-- -----------------------------------------------------------------------------
--
-- Copyright (C) 1999 Lars Larsson, Dept. of Computer Science
--                                  University of Hamburg
--                                  Vogt-Koelln-Str. 30
--                                  D - 22041 Hamburg, Germany
--                                  larsson@informatik.uni-hamburg.de
--                                  http://tech-www.informatik.uni-hamburg.de/~larsson
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
-- -----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity glue is
  port(       
                      clk :    in std_ulogic;                       -- clock = 16 MHz
                     nrst :    in std_ulogic;                       -- *reset

            nsend_receive :    in std_ulogic;                       -- (0:send,1:receive)

       rs232receiver_busy :   out std_ulogic;                       -- to HOLD input of RS232 receiver/text / text buffer
    rs232receiver_request :    in std_ulogic;                       -- from send output of RS232 receiver / text buffer
      rs232receiver_idata :    in std_ulogic_vector ( 7 downto 0);  -- from data byte output of RS232 receiver

         rs232sender_hold :    in std_ulogic;                       -- from busy output of RS232 sender
         rs232sender_send :   out std_ulogic;                       -- to request input of RS232 sender
        rs232sender_odata :   out std_ulogic_vector ( 7 downto 0);  -- to data byte input of RS232 sender
     
                  to_flex :   out std_logic;                        -- TriState IO contol for FLEXs
              flex_iodata : inout std_logic_vector  ( 7 downto 0);  -- TriState bus between EPLD, FLEXA, FLEXB

                flex_busy :   out std_logic;                        -- to hold input of FLEX
             flex_request :    in std_logic;                        -- from send output of FLEX
                flex_hold :    in std_logic;                        -- from busy output of FLEX 
                flex_send :   out std_logic                         -- to request input of FLEX
       );
end glue;

architecture behavior of glue is

   signal to_flex_s : std_logic;

   begin

     rs232receiver_busy <= flex_hold;
       rs232sender_send <= flex_request;
    
     to_flex_s <= rs232receiver_request; 
     to_flex   <= to_flex_s;

     flex_send <= to_flex_s;
     flex_busy <= rs232sender_hold; 

     tristate_p : process ( to_flex_s, rs232receiver_idata ) 
                  begin
                    if (to_flex_s='1') then
                        flex_iodata <= To_StdLogicVector(rs232receiver_idata);
                    else 
                        flex_iodata <= (others=>'Z');
                    end if;
                  end process;

                  rs232sender_odata <= To_StdULogicVector(flex_iodata);

   end behavior;

-- -----------------------------------------------------------------------------

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