Index of /vhdl/models/convolver

      Name                   Last modified     Size  Description


[DIR] Parent Directory       23-Feb-99 14:11      -  
[   ] acc12l.nmc             22-Jun-95 21:21     3k  
[   ] acc8.nmc               20-Jun-95 20:14     2k  
[   ] convolver.news         08-Sep-95 11:57    11k  
[CMP] convolver.tar.gz       08-Sep-95 13:46     7k  
[   ] filt.prf               27-Jun-95 21:27     1k  
[   ] filt.twr               10-Jul-95 15:29     7k  
[   ] filt.vhd               08-Aug-95 04:27    13k  
[   ] my_stuff.vhd           16-Jun-95 16:38     2k  
[   ] sreg4.nmc              20-Jun-95 21:17     1k  

Due to popular demand, I am posting the (Exemplar) VHDL source code for a
5X5 8 bit image convolver implemented in an ORCA 2C04 FPGA.  This was done
as a proof of concept design, and has not been simulated at a behavioral or
gate level.  (and thus is likely to contain bugs.) The Neocad hard macros
are also included, as well as a small package to define procedures for
synchronous write-enable flip flops.  The preference file (router
constraints & goals) is set for an aggressive 85 MHz clock frequency, but
the best that can actually be achieved (worst case over temp, process &
voltage) is around 81.8 MHz. 

The design uses no more than 2 levels of logic between flip flops, and
avoids routing congestion by using ROMS instead of RAMS for the lookup
tables.  (ROMS don't need control lines).  



John McCluskey

J.McCluskey@ieee.org