What is Verilog?

Verilog is a Hardware Description Language; a textual format for describing electronic circuits and systems. Applied to electronic design, Verilog is intended to be used for verification through simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic synthesis.

The Verilog HDL is an IEEE standard - number 1364. The standard document is known as the Language Reference Manual, or LRM. This is the complete authoritative definition of the Verilog HDL.

IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is a collection of software routines which permit a bidirectional interface between Verilog and other languages (usually C).

One important note: Don’t confuse Verilog HDL with the Verilog-XL family of simulators. In the mid-80’s, Gateway Design Automation developed a logic simulator, Verilog-XL, to simulate designs described using their proprietary Verilog HDL. Cadence have since bought Gateway and retained the Verilog-XL simulator, but the language, Verilog HDL, is now maintained by Open Verilog International (OVI). More on Verilog’s history in the next Backgrounder article. In all of the pages on this Web site, when we refer to Verilog, we mean the HDL not the simulator.

Today, there is one and only one Verilog HDL. There are now many Verilog-related EDA tools available: formal verification tools, cycle-based simulators, logic synthesisers, timing analysers and ESDA design entry tools with Verilog support. There are of course slight differences between these tools in the aspects of the Verilog HDL that are supported. Not all simulators support the full Verilog HDL, for example.

Finally, VHDL is not an abbreviation for Verilog HDL — Verilog and VHDL are two different HDLs. They have more similarities than differences, however.

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