Scope of VHDL

VHDL is suited to the specification, design and description of digital electronic hardware.

System level
VHDL is not ideally suited for abstract system-level simulation, prior to the hardware-software split. Simulation at this level is usually stochastic, and is concerned with modelling performance, throughput, queueing and statistical distributions. VHDL has been used in this area with some success, but is best suited to functional and not stochastic simulation.

Digital
VHDL is suitable for use today in the digital hardware design process, from specification through high-level functional simulation, manual design and logic synthesis down to gate-level simulation. VHDL tools usually provide an integrated design environment in this area.

VHDL is not suited for specialized implementation-level design verification tools such as analog simulation, switch level simulation and worst case timing simulation. VHDL can be used to simulate gate level fanout loading effects providing coding styles are adhered to and delay calculation tools are available. The standardization effort named VITAL (VHDL Initiative Toward ASIC Libraries) is active in this area, and is now bearing fruit in that simulation vendors have built-in VITAL support. More importantly, many ASIC vendors have VITAL-compliant libraries, though not all are allowing VITAL-based sign-off — not yet anyway.

Analogue
Because of VHDL's flexibility as a programming language, it has been stretched to handle analog and switch level simulation in limited cases. However, look out for future standards in the area of analog VHDL. Check out our Model of the Month from April 1996 for an example of analogue modeling in VHDL.

Design process
The diagram below shows a very simplified view of the electronic system design process incorporating VHDL. The central portion of the diagram shows the parts of the design process which are most impacted by VHDL.

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