Model of the Month

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Simple RAM Model

This month, a simple RAM model, written in Verilog. Following on from last month’s introduction to parameterisation, the RAM model presented here is parameterisable in terms of memory depth and wordlength. Memory depth is parameterised using the AddressSize parameter, whilst WordSize is used to parameterise the wordlength.

The declaration,

reg [WordSize-1:0] Mem [0:1<<AddressSize];

defines the size of the memory block. Note the use of the << operator to provide a convenient mechanism for implementing 2N; there is no exponentiation operator in Verilog as there is in VHDL.

Just like the shift register model from November, the parameterisable bidirectional port is modelled as a conditional assignment. This assignment effectively models the read process from the RAM.

The first always block models the write process. The second provides a simple simultaneous read-write check.

Note that it is not possible address individual bits in the memory block using two-dimensional addressing as in VHDL. In Verilog, you need to create a temporary reg object for the memory word and then access a bit or a bit-select from that temporary reg object.

Oh, yes. How about a timing diagram?

You are welcome to use the source code we provide but you must keep the copyright notice with the code (see the Acknowledgements page for more details).

// RAM Model
//
// +-----------------------------+
// |    Copyright 1996 DOULOS    |
// |       Library: Memory       |
// |   designer : John Aynsley   |
// +-----------------------------+
 
module RamChip (Address, Data, CS, WE, OE);

parameter AddressSize = 1;
parameter WordSize = 1;

input [AddressSize-1:0] Address;
inout [WordSize-1:0] Data;
input CS, WE, OE;

reg [WordSize-1:0] Mem [0:1<<AddressSize];

assign Data = (!CS && !OE) ? Mem[Address] : {WordSize{1'bz}};

always @(CS or WE)
  if (!CS && !WE)
    Mem[Address] = Data;

always @(WE or OE)
  if (!WE && !OE)
    $display("Operational error in RamChip: OE and WE both active");

endmodule

VHDL and Verilog source code for other Models of the Month
can be downloaded from here.

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Model of the Month

Simple RAM Model

VHDL and Verilog source code for other Models of the Month can be downloaded from here.

VHDL and Verilog source code for other Models of the Month
can be downloaded from here.