The following quiz will allow you
to test your knowledge about the VHDL language and its application domains.
The questions are generated from a predefined questions - answers
basis located at our server. The "quiz" applet generates several
categories of questions including:
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questions for yes-no answer
e.g. any VHDL description must contain at least one entity
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questions for multiple choice answer
e.g. how many architectures can be associated with an entity ?
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one or more
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more than one
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only one
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none
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phrases with holes
e.g. the ... cannot be declared inside process unit
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variables
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signals
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constants
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functions
load the quiz
The quiz framework has been prepared by Remi Jannic (IRESTE)
Note:
New questions will be added constantly to the query-answer base.
If you have some examples of new questions (answers) please contact:
pbakowsk@ireste.fr